[1]李俊霣「類比CMOS積體電路設計」 Behzad Razavi McGraw-Hill 2002,6
[2]羅正鐘、張鼎張 「半導體製程技術導論」” introduction to Semicondutor
Manufacturing Technology Hong Xiao 2002,8(2)
[3]國家晶片系統設計中心(CIC)訓練課程Verilog-HDL 設計 Xilinx FPGA,
設計流程課程參考。
[4]國家晶片系統設計中心(CIC)”Workshop on Fully Layout Technology MIXED
SIGNAL IC LAYOUT NOVATEK Layout Engineering Department” Johnson
Liu 2002 / 03 / 23課程參考。
[5]陳伯奇教授主講-財團法人自強工業科學基金會96年度通訊電子人才培訓
計畫講義【96S087 CMOS類比積體電路佈局原理與技術96/4/27】
[6]陳伯奇教授主講-財團法人自強工業科學基金會95年度通訊電子人才培訓
計畫講義【95S071 類比混合積體電路設計95/3/2】
[7]張宜恆 「上提式離散小波硬體設計」。南台科技大學電子工程研究所碩士論文。民國92年6月。
[8]鄭家賢「高效能上提式離散小波轉換硬體架構之設計與實現」。南台科技大
學電子工程研究所碩士論文。民國91年6月。
[9]陳雍岱。「餘數系統之JPEG2000上提式離散小波順/逆像轉換硬體架構設計
與VLSI 實現」。雲林科技大學電子與資訊工程研究所碩士論文。民國92年。
[10]陳央霖。「一維多階可調離散小波轉換之積體電路設計」。中華技術學院電子
工程研究所碩士論文。民國98年。
[11]Aan Hstings,“The Art of analong layout,” 2001 by prentice hall upper saddle river, NJ07458”
[12]K. G. Oweiss, “A systems approach for data compression and latency reduction
in cortically controlled brain machine interfaces,” IEEE Tran. on Biomed. Eng.,vol. 53, no. 7, pp. 1364-1377, 2006。
[13]Kamboh,A.M ; Raetz, M ; Mason,A ; Oweiss, K,
“Area-Power Efficient Lifting-Based DWT Hardware for Implantable Neuroprosthetics”, Circuits and Systems, Symposium on Volume , Issue , pp。2371–2374, 27-30 May 2007
[14]Kamboh , A.M.Raetz, M.Oweiss, K.G. Mason, A. “Area-Power Efficient VLSI Implementation of Multichannel DWT for Data Compression in Implantable Neuroprosthetics” Biomedical Circuits and Systems, IEEE Transactions on Volume 1, Issue 2, pp.128 – 135, June 2007
[15]W. Sweldens, “The lifting scheme: A construction of second-generation wavelets,” SIAM J. Mathematical Analysis, vol. 29, no.2, pp. 511–46, 1997.
[16]Stephane G. Mallat, “Multifrequency Channel Decompositions of Images and Wavelet Models,” IEEE Trans.on Acoustics, Speech, Signal Processing, 1989.
[17]W. Sweldens, “The lifting scheme: A construction of second-generation wavelets,” SIAM J. Mathematical Analysis, vol. 29, no.2, pp. 511–46, 1997.
[18]Aroutchelvame S.M. , K. Raahemifar, “AN EFFICIENT ARCHITECTURE FOR LIFTING-BASED FORWARD AND INVERSE DISCRETE WAVELET TRANSFORM,” Multimedia and Expo, 2005. ICME 2005. IEEE International Conference on, pp. 816 – 819, 2005.
[19]C. Sidney Burrus, Ramesh A. Gopinath, Haitao Guo. ”Introduction to Wavelets and Wavelet Transforms A Primer,” Prentice Hall, 1998.
[20]Jer-Min Jou,Yeu-Horng Shiau,Chin-Chi Liu, “EFFICIENT VLSI ARCHITECTURES FOR THE BIORTHOGONAL WAVELET TRANSFORM BY FILTER BANK AND LIFTING SCHEME,” Circuits and Systems, IEEE International Symposium on, vol. 2, pp. 529-532, 2001.
[21]P. Y. Chen, “VLSI implementation for one-dimensional multilevel lifting-based wavelet transform,” IEEE Trans.on Computers, vol.53, no.4, pp.386-398, April 2004.