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研究生:何家瑋
研究生(外文):Chia-Wei Ho
論文名稱:熱電子注入對非重疊佈植記憶元件之資料保存能力研究
論文名稱(外文):Study on NOI Memory Device Retention under Hot Electron Injection
指導教授:鄭湘原
指導教授(外文):Erik S. Jeng
學位類別:碩士
校院名稱:中原大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:71
中文關鍵詞:資料保存非揮發性記憶體
外文關鍵詞:NVMData retention
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半導體製程技術的精進使得半導體非揮發性記憶體亦逐年在進步。隨著元件的微縮,具功率消耗低、元件密度高、操作速度快、且相容於CMOS邏輯製程的記憶元件將是未來發展的趨勢。
本論文以熱電子對新型非重疊式離子植入金氧半場效電晶體之資料保存為研究主題,此記憶元件的寫入係利用通道熱電子注入,並以兩側壁區作為個別位元儲存之區域。透過Arrhenius equation 預測不同溫度下的保存時間。並利用實際量測的電荷幫浦(Charge Pumping)方式計算出電荷流失之情況,最後,透過藉由改變寫入電壓去探討,不同寫入電壓對於資料保存的影響。




The non-volatile semiconductor memories have rapidly progressed as the semiconductor technologies advance. The memory devices having low power consumption, high density, high-speed operation, and full compatibility with the standard CMOS processing will be the future development trend in non-volatile memories.
This work explores the data retention of trapped electrons in the Non-overlapped Implantation (NOI) MOSFETs. As potential non-volatile memories, the NOI devices can be programmed by channel hot electron injection. By Arrhenius equation, the charge loss with time has been modeled and predicted under elevated temperatures. The charge loss in the nitride was also measured using a modified charge pumping method. Data retention characteristics with different programming conditions were studied. Finally, the trend of charge loss in the NOI devices is affected by different program biases.




中文摘要 I
Abstract II
Acknowledgments III
Contents IV
Figure Captions VI
Table Captions VIII
第一章 非揮發性記憶元件之資料保存實驗介紹 IX
第二章 非揮發性記憶體中之操作機制及資料保存分析 X
第三章 新型非揮發性快閃記憶體之資料保存模型建立 XI
第四章 新型非揮發性快閃記憶體之資料保存特性分析 XII
第五章 結論及未來展望 XIII
Chapter 1 Retention Characteristics of Non Volatile Memory Devices 1
1-1 Introduction 1
1-2 Flash Memory Data Retention 4
1-2-1 Activation Energy and Temperature-Accelerated method 4
1-3 Charge Loss Mechanisms in NVM 6
1.3.1 Intrinsic Charge Loss 6
1.3.2 Charge Loss Due to Oxide Defect 7
1.3.3 Charge Loss through ONO 7
1.3.4 Charge Loss Due to Contamination 8
1-4 Organizations of This Thesis 9
Chapter 2 NVM Operations and Related Retention Issues 10
2-1 Introduction 10
2-2 Hot Carrier Effect (HCE) 11
2-3 Fowler-Nordheim (FN) Tunneling 14
2-4 The Hot Holes Enhanced Injection 16
2-5 Band to Band tunneling (BTBT) 16
2-6 Data Retention Issues 18
2-6-1 Program mechanism induced charge leakage 18
2-6-2 Erase mechanism cause charge leak 21
2-7 Summary 23
Chapter 3 Retention Model of NOI Memory Devices 24
3-1 The Process Flow 24
3-2 NOI Memory Device Operation 27
3-2-1 Programming 28
3-2-2 Reading 29
3-2-3 Forward Read 30
3-2-4 Reverse Read 31
3-3 The Retention Characterization of NOI Device 32
3-4 Retention Model of NOI Devices 34
3-5 Summary 38
Chapter 4 Field-Dependant Data Retentionof NOI Memory Device 39
4-1 The Measurement System 39
4-2 Charge Pumping Experiment Measurement 40
4-3 Data Retention with Different Program Condition 46
4-4 Summaries 51
Chapter 5 Conclusions and Future Work 52
5-1 Conclusions 52
5-2 Future Work 52
Reference 54
個 人 自 傳 58

Chapter 1 The Retention Experiment of Non Volatile Memory
Fig. 1- 1 Schematic cross section of floating gate device...........................1
Fig. 1- 2 Schematic cross section of NROM device...................................2
Fig. 1- 3 Erase state and program state current-voltage characteristics3
Fig. 1- 4 Arrhenius diagram at various temperatures..............................5
Fig. 1- 5 E-I characteristics for inter-poly ONO film with various top-oxide thickness [1-5]......................................................................8
Chapter 2 The Retention With Different High Field Operations in NVMs
Fig. 2- 1 The Hot-Carrier Effect generation............................................12
Fig. 2- 2 The mechanisms of hot carriers inject into oxide....................13
Fig. 2- 3 The energy band diagram for electrons transport through the Si/SiO2 potential barrier from the Si conduction band into SiO2 conduction band. (a)FN Tunneling (b)Directly Tunneling.............14
Fig. 2- 4 The energy band diagram for a positive bias is applied to the gate and electrons transport through the triangular Si/ SiO2 potential barrier from the Si conduction band into SiO2 conduction band.....................................................................................................15
Fig. 2- 5 The hot hole enhance injection is used as the erasing mechanism of NROM device.............................................................16
Fig. 2- 6 The Schematic of the hot hole injection generated by Band-to –Band Tunneling..................................................................17
Fig. 2- 7 Schematic representation of the location of oxide traps and interface states generated by CHE injection...................................19
Fig. 2- 8 Illustration of nitride trapped charge escape by Frenkel -Poole emission and subsequently oxide trap assisted tunneling..............20
Fig. 2- 9 J-E characteristics of capacitors having 51 to 91 Å oxide before and after charge injection stress[2-11].............................................21
Chapter 3 The Retention Model of NOI Memory Device
Fig. 3- 1 The schematic process flow of a NOE NVM device.................27
Fig. 3- 2 The schematic cross section of that a NOE NVM device uses CHEI as the programming mechanism...........................................29
Fig. 3- 3 The read directions of a NOI NVM device...............................30
Fig. 3- 4 The schematic cross section of forward read bit-1 of the NOI device, and electrons can travel through the trapped charge region easily as increasing the drain voltage...............................................31
Fig. 3- 5 The schematic cross section of reverse read bit-1 of the NOIdevice...................................................................................................32
Fig. 3- 6 Data retention characteristic of NOI device.............................33
Fig. 3- 7 Threshold voltage drop vs. varying Baking temperature........34
Fig. 3- 8 The fitting results of Data retention characteristic of a NOI device...................................................................................................36
Fig. 3- 9 Leakage paths are elucidated in the energy-band diagram....37
Chapter 4 The Data Retention of NOI Memory Device
Fig. 4- 1 The installation of NOI measurement system..........................40
Fig. 4- 2 The experiment setup for charge pump measurement............41
Fig. 4- 3 The Icp curve at erased state (a) Drain-side. (b) Source-side.44
Fig. 4- 4 Charge loss in the nitride by Icp measurement........................46
Fig. 4- 5 Programming speed characteristics of NOI n-MOSFETs......47
Fig. 4- 6 The characteristics of data retention with drain voltage change form 4V to 6V and Vg fixed 9V........................................................48
Fig. 4- 7 The characteristics of data retention with gate voltage change form 7V to 9V and Vd fixed 6V........................................................49
Fig. 4- 8 Charge loss ratio vs. different program condition...................50

Chapter 1 The Retention Experiment of Non Volatile Memory
Table 1- 1 charge loss mechanisms and the association with activation energies.............................................................................................6
Chapter 2 The Retention With Different High Field Operations in NVMs
Table 2- 1 The programming/ erasing mechanism in NVMs.................10
Chapter 4 The Data Retention of NOI Memory Device
Table 4- 1Operation conditions of the NOI Device as an NVM.............42
Table 4- 2Program conditions of the NOI Device...................................48
Table 4- 3 The ratio of Vth drop of the data retention experiment.......49
Chapter 1

[1-1] W. D. Brown, and J. E. Brewer, Nonvolatile Semiconductor Memory Technology, IEEE Press, 1998.
[1-2] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memory, Kluwer Academic Publishers, 1999.
[1-3] W. D. Brown, and J. E. Brewer, Nonvolatile Semiconductor Memory Technology, IEEE Press, 1998.
[1-4] R.Shiner, J. Caywood, and B. Euzent, “Data Retention in EPROMs, ”Proc. IRPS, p.145, 1980.
[1-5]K. Wu, C. S. Pan, J. J. Shaw, P. Freiberger, and G. Sery, “A Model for EPROM Intrinsic Charge Loss through Oxide-Nitride-Oxide (ONO) Interpoly Dielectric,” Proc. IRPS, p.145, 1990.

Chapter 2

[2-1]E. J. Prinz, G. L. Chindalore, K. Harber, C. M. Hong, C. B. Li, and C. T. Swift, “An Embedded 90nm SONOS Flash EEPROM Utilizing Hot Electron Injection Programming and 2-Sided Hot Hole Injection Erase”, NVM 2003 Nonvolatile Memory Workshop.
[2-2]Y. Taur and T. H. Ning, “Fundamentals of Model VLSI Device”, p.913
[2-3]C. Y. Chan, S. M. Sze, “ULSI DEVICES”, p.275
[2-4]E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Characterization of Channel Hot Electron Injection by the Subthreshold Slop of NROMTM Device”, IEEE Electron Device Lett., Vol.22, p.556, 2001.
[2-5] Luca Selmi and David Esseni, “A Better Understanding of Substrate Enhanced Gate Current in VLSI MOSFET’s and Flash Cells-Part II: Physical Analysis”, IEEE Trans. Elec. Device, vol.46, NO.2, pp.376~pp.381, February 1999
[2-6] K. R. Hofmann, C. Werner, W. Weber, AND G. Dorda, “Hot-Electron and Hole-Emission Effects in Short n-Channel MOSFET‘s,” IEEE Trans. Elec. Device, vol.32, NO. 3, pp. 691-699, MARCH 1985.
[2-7] O. Semenov, A. Pradzynski, and M. Sachdev, “Impact of Gate Induced Drain Leakage on Overall Leakage of Submicrometer CMOS
[2-8] T. Y. Chan, J. Chan, P. K. Ko, and C. Hu, “The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,” IEEE IEDM, Vol. 33, pp. 718-721, 1987.
[2-9]C. M. Yih, Z. H. Ho, M. S. Liang, “Characterization of Hot-Hole Injection Induced SILC and Related Disturbs in Flash Memories”, IEEE Trans. Elec. Device, vol.48, No.2, Feb. 2001.
[2-10] T. Wang, N. K. Zous, J. L. Lai, and C. Huang, “Hot hole stress induced leakage current (SILC) transient in tunnel oxide”, IEEE Electron Device Lett., vol.19, pp. 411-413, 1998

[2-11] R. Moazzami and C. Hu, “Stress-Induced Current in Thin Silicon Dioxide Films,”IEEE IEDM Tech. Dig., p.139,1992
[2-12] J. Maserjian and N. Za,ani, “Observation of positively charged state generation near the Si/SiO2 interface during Fowler-Nordheim tunneling”, J. Vac. Sci. Technol., vol. 20, pp. 743-764, 1982
[2-13] R. Rofan and C. Hu, “Stress-induced oxide leakage”, IEEE Electron Device Lett., vol. 12, pp. 632-634, 1991
[2-14] R. Moazzami and C. Hu, “Stress-induced current in thin silicon dioxide films”, in IEDM Tech. Dig., 1992, pp.139-142.
[2-15] R. S. Scott and D. J. Dumin, “The Charging and dischatging of high-voltage stress-generated traps in thin silicon oxide”, IEEE Tran. Electron Devices, vol.43, pp.130-136, 1996

Chapter 3

[3-1] H. Lee, S. Chang, J. Lee and H. Shin, “Characteristics of MOSFET with Non-overlapped Source-drain to Gate”, IEICE Trans. Electron, Vol. E85-C, No. 5, pp. 1079-1085, 2002.
[3-2] F. Matsuoka, H. Hayashida, K Hama, Y. Toyoshima, H. Iwai and K. Maeguchi, “Drain Avalanche Hot Hole Injection Mode on PMOSFETs”, IEEE IEDM, pp.18~pp.21, 1998
[3-3]T. Y. Chan, K. K. Young and C. Hu, “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device”, IEEE Electron Device Letters, VOL. EDL-8, NO.3, pp.93~pp.95, March 1987
[3-4]B. Eitan, “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping”, U.S. Patent 6,011,725, Jan.4 2000
[3-5] J. H. Kim and J. B. Choi, “Long-Term Electron Leakage Mechanisms Through ONO Interpoly Dielectric in Stacked-Gate EEPROM Cells,” IEEE Trans. Electron Devices, vol. ED-51, no.12, pp.2048–2053, Dec. 2004.
[3-6] R. A. Williams and M. M. E. Beguwala, “The effect of electrical conduction of Si3N4 on the discharge of MNOS memory transistors,” IEEE Trans. Electron Devices, vol. ED-25, no. 8, pp. 1019–1023, Aug. 1978.
[3-7] L. Lundkvist, I. Lundstorm, and C. Svensson, “Discharge of MNOS structures,”Solid State Electron., vol. 16, no. 7, pp. 811–818, Jul.

Chapter 4
[4-1] E.S. Jeng, P.C. Kuo, C.S. Hsieh, C.C. Fan, K.M. Lin, H.C. Hsu, W.C. Chou, “Investigation of Programming Charge Distribution in Nonoverlapped Implantation nMOSFETs,” IEEE Transactions Electron Devices, vol. 53, No. 10, pp. 2517-2524, 2006.
[4-2]C. Chen and T. P. Ma, “Direct Lateral Profiling of Hot-Carrier-Induced Oxide Charge and Interface Traps in ThinGate MOSFET’s”, IEEE Trans. Electron devices, Vol.45, No.2, pp.512-520, Feb. 1998.
[4-3]A. M. Martirosian and T. P. Ma, “Lateral Profiling of Interface Traps and Oxide Charge in MOSFET Devices: Charge Pumping Versus DCIV”, IEEE Trans. Electron devices, Vol.48, No.10, pp.2303-2309, Oct. 2001.
[4-4]K. Suuki, “Parasitic Capacitance of Submicrometer MOSFET’s,” IEEE Trans. Elec. Device, vol.46, No. 9, pp. 1895-1900, SEPTEMBER 1999.

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