臺灣博碩士論文加值系統

近年來使用者的需求提高，應用程式更為複雜，許多嵌入式系統使用作業系統來幫助管理，同時也使用虛擬記憶體架構來彌補嵌入式系統資源上的不足。然而，當虛擬記憶體的架構被採用時，快取的設計可分為兩種 1) physical cache與2) virtual cache，針對第一種，快取內是使用實體位址來存放，因此，在存取前必需進行虛擬位址與實體位址之間的轉換，然而，轉換過程將會使指令存取時間拉長與限制快取的容量。另外，第二種設計，虛擬位址可直接存取快取，不需進行轉換，然而，這種設計將導致同名的問題發生。因此，如何設計一個虛擬記憶體架構可縮減指令存取的時間、且無容量的限制與無同名問題將是我們設計的重點。在本篇論文中，我們將提出兩個新的virtual cache設計，分別針對效能與電能進行改良，在實驗模擬中，以效能為考量的方法在使得整體架構效能平均提升31%，並且在電能考量的架構中，可以節省約27%的電能，使得更適合於嵌入式系統中。

In recent years, the demand of user are increasing, and the application are more and more complex, many embedded device start used operation system and virtual memory to help manage. However, when virtual memory is used, there are two kind of cache architecture: 1) physical cache and 2) virtual cache. For the first, the cache is access by physical address, therefore, cache before the access must be translation the virtual address to physical address, however, the translation is a waste of time and limit the capacity of cache. For the second design, virtual address can access the virtual cache immediate without translation to reduce the time; however, the virtual cache will access the wrong data by the synonym problem. Therefore, how to design the virtual cache architecture can reduce time, no capacity limited and no synonym problem will be focus of our design. In this paper, we will present two virtual cache designs, respectively, for the performance and power. In the experimental simulation, in the performance, taking into consideration the design of the virtual cache, the overall structure of performance improvement of about 31%, and energy considerations in the design, it can save about 27% of energy consumption. We design the virtual cache is more suitable for embedded systems.

誌謝................................................................................................................................i
Abstract.......................................................................................................................iii
目錄...............................................................................................................................iv
圖目錄...........................................................................................................................v
表目錄..........................................................................................................................vi
第一章 緒論.................................................................................................................1
1.1 研究背景........................................................................................................1
1.2 研究動機........................................................................................................1
1.3 研究目標與研究方法....................................................................................4
1.4 本文架構........................................................................................................5
第二章 相關研究.........................................................................................................6
2.1 省電及快速的TLB架構..............................................................................6
2.2 虛擬快取架構................................................................................................7
第三章 快速存取與省電的虛擬快取設計.................................................................9
3.1 快速存取的V/P快取..................................................................................10
3.1.1 快取失誤時利用實體位址回放.......................................................10
3.1.2 透過作業系統解決存取與回放位置不一致...................................11
3.1.3 提出的方法的影響...........................................................................12
3.1.3.1 限制分頁配置........................................................................12
3.1.3.2 同名位址................................................................................12
3.2 省電的V/V快取..........................................................................................14
3.2.1 透過檢查位元避免快取中出現多個同名的位置...........................14
3.3.2 透過增加欄位以減少無效區塊的數量...........................................16
第四章 模擬結果與分析...........................................................................................17
4.1 模擬環境與參數..........................................................................................17
4.2 實驗結果......................................................................................................18
4.2.1 效能比較............................................................................................18
4.2.2 電能比較............................................................................................20
4.2.3其他比較.............................................................................................21
第五章 結論...............................................................................................................23

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