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研究生:黃俊源
研究生(外文):Chen-Yuen Huang
論文名稱:動量估測運算陣列之可測試性與內建自我測試架構
論文名稱(外文):Testable and BIST Architectures for Motion Estimation Computing Arrays
指導教授:呂學坤
指導教授(外文):Shyue-Kung Lu
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:98
語文別:中文
論文頁數:65
中文關鍵詞:動量估測
外文關鍵詞:Motion Estimation
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動量估測 (Motion Estimation) 是影像編碼系統中最主要的運算,是運算量最為密集的一個部分,也因為簡單性和規律性,區塊比對演算法被廣泛的應用在運動向量的計算上。而因現今VLSI 技術的進步,使得動量估測運算陣列得以整合到系統晶片 (SOC, System-on-a-chip) 上。然而,因為系統晶片的腳位有限,將會大大的降低其晶片測試的效率。為了解決這樣的問題,使測試能快速且有效的進行,因此必須對動量估測運算陣列進行可測試性與內建自我測試的硬體電路設計。基於C-testability關係,在位元階層下,將動量估測運算陣列之基本細胞 (cell) 之功能調整成具有 bijective 的特性。在模組階層下,由於它本身的輸入皆能由外部控制,輸出也都能傳到最主要的輸出端,故電路本身即具有可控制性與可觀測性。在內建自我測試的設計中,我們使用計數器作為測試向量產生器;在輸出響應分析器方面,則利用查驗總和的方式來驗證。在位元階層下,我們只需要32組的測試向量;在模組階層下,則需要2w組測試向量來完成。在內建自我測試的架構中,需要的額外硬體成本約為2%。另外由於在單一細胞下進行DFT設計時,其硬體成本較高,因此我們也提出模組化 (Scalable) 之可測試性技術,以期在測試向量數目與硬體成本間作取捨,我們也以動量估測陣列與快速傅立葉轉換器陣列來驗證我們的想法。
Motion estimation is the main computation used in video coding systems. It’s the most computation-intensive part. Because of the simplicity and regularity, the block matching algorithms are widely used for the computation of motion vectors. With the advance of VLSI technology, integration of the motion estimation computing array into a single chip or a system-on-chip (SOC) design is becoming possible. However, integrating a large number of processing elements (PEs) on a single chip or SOC will increase the logic-per-pin ratio, which drastically reduces the efficiency of testing the logic on the chip. In order to deal with these problems, design-for-testability and BIST techniques are proposed for motion estimation computing arrays. The bit-level or word-level cells (modules) in the array are made bijective to meet the C-testability conditions. The test pattern generator can be a simple binary and the output response analyzer is basically a checksum comparator. The number of test patterns is 32 and 2w for the bit-level and module-level designs, respectively. The hardware overhead of the BISTed motion estimation array is only 2 %. In order to tradeoff between the hardware overhead and the number of test patterns, a scalable DFT technique was also proposed in this thesis.
中文摘要‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ i
英文摘要‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ ii
致謝‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iii
目錄‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iv
表目錄‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ vi
圖目錄‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ vii
第一章 緒論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.1 動機‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1.2 論文架構‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 4
第二章 動量估測演算法與架構分析‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 5
2.1 固定區塊比對演算法‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 5
2.1.1 完全搜尋演算法‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 6
2.1.2 三步搜尋演算法‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 7
2.1.3 新三步搜尋法‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 8
2.2 可變式區塊比對演算法 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧9
2.3 區塊大小比對演算法之硬體架構設計‧‧‧‧‧‧‧‧‧‧‧‧‧10
2.3.1 固定式區塊大小比對演算法架構‧‧‧‧‧‧‧‧‧‧‧‧‧10
2.3.1.1 Komarek 和 Pirsch 的架構‧‧‧‧‧‧‧‧‧‧‧‧10
2.3.1.2 Yeo 和 Hu 的架構‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧11
2.3.2 可變式區塊大小比對演算法架構‧‧‧‧‧‧‧‧‧‧‧‧12
第三章 動態估測架構之可測試性設計回顧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 14
第四章 動量估測陣列之可測試性設計‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 17
4.1 C-testability 相關觀念回顧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 17
4.2 位元階層 (Bit Level) 之可測試性設計‧‧‧‧‧‧‧‧‧‧‧‧‧ 20
4.3 模組階層 (Module Level) 之可測試性設計‧‧‧‧‧‧‧‧‧‧‧ 25
第五章 動量估測陣列之內建自我測試性設計‧‧‧‧‧‧‧‧‧‧‧‧‧ 29
第六章 連續邏輯陣列的模組化可測試性設計‧‧‧‧‧‧‧‧‧‧‧‧‧‧34
6.1 主要目的‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 34
6.2 模組化架構設計‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧34
6.2.1 全加法器的模組化架構設計‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧36
6.2.2 動量估測陣列的模組化架構設計‧‧‧‧‧‧‧‧‧‧‧‧‧38
6.2.3 快速傅立葉轉換器 (FFT) 的模組化架構設計‧‧‧‧‧‧‧‧42
第七章 實驗結果‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 52
7.1 設計流程‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 52
7.2 模擬結果‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 55
7.3 失真機率‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧58
7.4 模組化比較‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧60
第八章 結論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧62
8.1 結論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 62
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