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研究生:莊宜豐
研究生(外文):Yi-Feng Zhung
論文名稱:改良型數位計算機座標演算法及電路架構應用於快速傅立葉處理器
論文名稱(外文):Design of Modified CORDIC Algorithms and Circuit Architectures for Fast Fourier Transform
指導教授:賴俊如
指導教授(外文):Jiunn-Ru Lai
學位類別:碩士
校院名稱:國立高雄應用科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:63
中文關鍵詞:數位計算機座標旋轉定義域摺疊正餘弦
外文關鍵詞:CORDICVerilogFPGA
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本論文中,我們針對快速傅立葉演算架構中的數位計算機座標旋轉演算法提出改良型定義域摺疊式暨查表補償誤差法數位計算機座標旋轉演算法(MFE-CORDIC)與硬體架構,以較快的運算方法來做出正、餘弦函數產生器。

為尋求演算速度和記憶體使用率上的平衡,在改良型數位計算機座標旋轉演算法的主體旋轉架構中使用11級旋轉運算,將兩級合為一階,在將三階合為一單元。透過只需3次疊代就可以完成11級運算,來減少四次疊代所產生的延遲,以提升電路的速度。後級使用查表補償架構,來補償前級運算的誤差及取代後5級角度運算。在旋轉座標的起始點,我們使用一定值,減少比例因子的產生時間和起點值的運算。

在這演算法中我們主要針對面積、運算延遲時間分別提出改善之道。在電路面積使用率改進,管線及角度分解架構共使用了22個移位器、22個加法器及在查表架構的記憶體補償查表使用208位元。另外,在運算延遲的改進方面,是將起始點採用定值,所以節省產生起點值的運算時間,且將主旋體電路管線、角度分解及查表架構三者搭配使用來減少疊代次數,提升運算速度。藉由以Verilog硬體描述語言設計及ModelSim模擬其結果,再藉由Xilinx virtex-II pro FPGA 實驗板與軟體 Xilinx ISE 10.1合成電路實現驗證其可行性。透過晶片輸出腳讀取信號,以驗證電路的實際計算值。
In this paper, we introduced the design of improved Modified CORDIC Algorithm using Domain Folding and Error Lookup Table (MFE-CORDIC) and hardware architecture on FFT algorithm, to generate the sine and cosine function by that efficiency algorithm.

To reach the balance between calculating speed and memory usage, the 11 rotating operation is used in the main rotary structure of modified coordinate rotation digital computer algorithms, the two merged into one order, then combine as a unit. In this design, 11 rotating operations can be completed through 3 iteration, circuit speed can be highly improved. In last steps, using look-up table structure to compensate for the error which generated from previous operations, then replace the error of last 5 steps point operations. In addition, we set a constant value for starting point of the rotating, to reduce the production time of scale factor from the value of computing and skip the calculation time of starting point.

In the algorithm, we present improve method for both circuit area measure -ment and calculation delay. For circuit area utilization improvement, pipeline and angel decomposition structure applied only total 22 shifters, 22 adders and 208 bit (the look-up table). Second, for computing delay improvement, we set a constant value at starting point, so to save the operation time of starting value, and to reduce the number of iteration and improve processing speed by adopting circuit lines, angle decomposition, and look-up table structure.

To realize this design, we used Verilog hardware describing language for design, Modelsim for simulating the results, and Xilinx virtex-II pro FPGA test board applied with Xilinx ISE 10.1 software synthesis circuit for verifying the feasibility. Finally, by analyzing signal generated from chip, we obtain the value.
摘要
ABSTRACT
誌謝
目錄
表目錄
圖目錄
一、 簡介
1. 1 序論
1. 2 研究動機與目的
1. 3 問題描述
1. 4論文架構
二、背景與相關研究
2. 1以CORDIC實現的正、餘弦波形產生器
2.1. 1座標旋轉運算
2.1. 2 基底為二的近似定理( The Radix-2 Approximating Theorem )
2.1. 3 CORDIC架構
2. 2 Similar CORDIC-Type I 演算法
2.2. 1冗餘進位節省演算法(Redundant Carry-Save Algorithm)
2.2. 2 Similar CORDIC-Type I 架構
2. 3 Similar CORDIC-Type II 演算法
2. 4 MDF-CORDIC演算法
2. 5 MEDF-CORDIC演算法
2. 6觀念使用及缺點改正
三、所提出之演算法和硬體設計
3. 1正、餘弦產生器架構
3.1. 1定義域折疊
3.1. 2管線架構
3. 2改良型定義域摺疊式暨查表補償誤差法數位計算機座標旋轉演算法
3.2. 1角度分割與前級運算
3.2. 2後級查表補償
3. 3 MFE-CORDIC電路架構(16bit)
3. 4未來工作
3. 5 MFE-CORDIC電路架構(32bit)
3. 6各演算法架構的差異
四、模擬結果
4. 1 MFE-CORDIC 之Modelsim模擬結果
4. 2二分法補償數學模擬
4. 3 FPGA 實現
五、結論與貢獻
5. 1結論
參考文獻
附錄
附錄1:程式
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