本研究中所設計的IIR數位積分器是根據複合辛普森積分規則和分數延遲濾波器。為了增進複合辛普森IIR數位積分器在高頻的設計準確性，我們的取樣週期減少到1/2T，1/4T，1/6 T，1/8T …等，我們需要設計一個分數延遲濾波器以增進複合辛普森IIR數位積分器之效能。 然而，當我們使用在FIR和全通分數延遲濾波器一個有大量資料佐證的設計技巧可以輕易的解決這些問題。文中有幾個設計例子說明我們提出的方法較有效率。

The IIR digital integrator is designed by using the Compound Simpson integration rule and fractional delay filter. To improve the design accuracy of a Compound Simpson IIR integrator at high frequency, the sampling interval is reduced from T to1/2T，1/4T，1/6 T，1/8T …. As a result, a fractional delay filter needed to be designed in the proposed Compound Simpson integrator. However, this problem can be solved easily by applying well-documented design techniques of the FIR and all-pass fractional delay filters. Several design examples are illustrated to demonstrate the effectiveness of the proposed method.

摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
表目錄 v
圖目錄 vi
第一章 簡介 1
1.1 研究動機 1
1.2 論文架構 1
第二章 複合辛普森積分法(Compound Simpson Rule) 2
2.1 複合辛普森積分器Compound Simpson Rule介紹 2
2.2 傳統辛普森積分器Simpson Rule介紹 3
2.3 辛普森積分器的傳統設計 4
2.4 辛普森積分器的進階設計 6
第三章 複合辛普森積分器的進階設計 10
3.1 2倍取樣率IIR Compound Simpson積分器設計 10
3.2 4倍取樣率IIR Compound Simpson積分器設計 17
3.3 6倍取樣率IIR Compound Simpson積分器設計 27
3.4 8倍取樣率IIR Compound Simpson積分器設計 41
第四章 結果與討論 58
4.1 各倍數取樣頻率的轉移函數 58
4.2 階數L=1,2,3之轉移函數的證明 59
4.3 各倍數取樣結果及誤差 66
第五章 結論 70
參考文獻 71

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