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研究生:陳奕辰
研究生(外文):Yi-Chen Chen
論文名稱:使用雜訊消除技巧之雙頻帶無線區域網路射頻前端設計
論文名稱(外文):The RF Front-End Design Using Noise Reduction Technique for Dual Band WLAN Applications
指導教授:江衍忠
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:93
中文關鍵詞:IEEE802.11a/b/g雙頻帶低雜訊放大器混波器主動巴倫電路雜訊抑制
外文關鍵詞:IEEE802.11a/b/gdual bandLNAMixeractive balunnoise reduction
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本論文探討使用雜訊抵銷技巧於802.11a/b/g雙頻帶無線射頻接收機的射頻積體電路設計以及系統整合概念。內容包含電路設計、系統分析、晶片量測、結果與討論。論文整體主軸可分為三大部分:第二章為低雜訊放大器、第三章為混波器及第四章的雙頻帶直接降頻整合接收機。
第二章的內容為低雜訊放大器設計。在此我們分析雜訊特性並且運用雜訊抑制的技巧設計一組雙頻帶低雜訊放大器。此電路使用TSMC 0.18 m CMOS製程製作。使用SB封裝並於PCB板量測情況底下,2.4GHz與4.7GHz量得之雜訊指數分別是4.4dB與4.6dB;功率增益則分別為9.3dB與11.2dB。此電路於1.8V偏壓下的直流功率消耗為16mW。
第三章為雙頻帶直接降頻混波器,分別使用TSMC 0.35 m SiGe BiCMOS製程及TSMC 0.18 m CMOS製程各完成一顆晶片。SiGe製程製作之晶片直接降頻至50MHz,量測結果雜訊指數20dB以下,功率轉換增益約5dB。此電路之功率轉換增益與線性度為近乎平衡的設計,以外並有良好隔離度。在3V操作電壓下,直流功率損耗為6mW。另一顆使用0.18 m CMOS製程設計之混波器亦降頻至50MHz,量得之雜訊指數約20dB,轉換增益約2dB;在1.8V操作電壓下,直流功率損耗為3.5mW。
第四章為應用於雙頻帶接收機之射頻前端電路,包含低雜訊放大器,主動巴倫電路,直接降頻混波器。此電路使用TSMC 0.18 m CMOS製程,於功率損耗25mW情況下,完成直接降頻50MHz,雙頻帶雜訊指數4dB以下,轉換增益於20dB以上,線性度高於-30dBm之模擬設計。


This thesis presents the receiver RFIC design for WLAN 802.11a/b/g dual band application using noise reduction technique in circuit design and system conception. This thesis is composed of three parts: low noise amplifiers (LNA), mixers, and the complete receiver front end. In each part, the content includes the circuit design, system analysis, chip measurement results, and a short discussion.
In chapter two, a LNA using noise reduction technique of dual band application which is implemented in TSMC 0.18 m process technology is presented. The on-bond measured NF for the proposed dual band LNA with SB package are 4.5dB and 6.8dB at frequencies 2.4GHz and 4.7GHz, respectively. The measured power gains are 9.3dB and 11.2dB at frequencies 2.4GHz and 4.7GHz, respectively. The power consumption of the proposed LNA is 16mW under 1.8V voltage supply.
In chapter three, a first mixer of direct down conversion system for dual band application is implemented in TSMC 0.35 m SiGe BiCMOS process technology. The on-wafer measured NF for the mixer of the dual band system is smaller than 20dB with IF at 50MHz. The power conversion gain is near 5dB at dual band of direct down conversion system. The measured data show good isolations and balance between linearity and power conversion gain. The dc power consumption is 6mW under 3V voltage supply. On the other hand, the second mixer of direct down conversion system for dual band application is implemented in TSMC 0.18 m CMOS process technology. The on-wafer measured NF for the mixer is smaller than 20dB with IF at 50MHz. The power conversion gain is near 2dB. The mixer consumes 3.5mW power from a 1.8V voltage supply.
In chapter four, a complete direct down conversion receiver RF front end for dual band application is presented. This circuit includes a dual band LNA, active balun circuits, and a direct conversion mixer, and it is designed in TSMC 0.18 m process technology. The front-end simulated NF is smaller than 4dB at dual band. The power conversion gain is more 20dB. The total power consumption is 25mW under 1.8V voltage supply.


誌謝 Ⅰ
摘要 Ⅱ
Abstract Ⅲ
目錄 Ⅳ
圖目錄 Ⅶ
表目錄 ⅩⅡ
第一章 緒論 1
1.1無線射頻系統背景 1
1.2無線射頻系統研究動機 2
1.3論文架構 3
第二章 應用雙頻帶低雜訊放大器 5
2.1低雜訊放大器簡介 5
2.1.1 簡介 5
2.1.2 雜訊指數 6
2.1.3 非線性效應—高階諧波 8
2.1.4 非線性效應—增益飽和 8
2.1.5 非線性效應—交互調變 9
2.1.6 電路架構穩定度 11
2.2 低雜訊放大器基本架構剖析 12
2.3 應用雙頻帶低雜訊放大器電路分析與設計 13
2.3.1 系統架構分析 13
2.3.2 論文回顧 13
2.3.3 電路架構匹配與雜訊指數分析和取捨 14
2.3.4 電路架構與雜訊分析 17
2.3.5 電路架構線性度 20
2.4 應用雙頻帶低雜訊放大器電路佈局圖 20
2.5 應用雙頻帶低雜訊放大器模擬與量測結果 21
2.5.1 模擬佈局 21
2.5.2 模擬結果 22
2.5.3 量測考量 24
2.5.4 量測結果 26
2.6 應用雙頻帶低雜訊放大器結果討論 31
第三章 混波器 33
3.1 簡介 33
3.2 混波器基本架構剖析 34
3.3 應用雙頻帶混波器電路分析與設計 35
3.3.1 系統架構分析 35
3.3.2 電路架構與雜訊分析 36
3.3.3 電路架構與線性度 38
3.3.4 SiGe 0.35μm電路架構 42
3.3.5 CMOS 0.18μm電路架構 43
3.4 應用雙頻帶混波器電路佈局圖 45
3.4.1 SiGe 0.35μm電路架構 45
3.4.2 CMOS 0.18μm電路架構 46
3.5 應用雙頻帶SiGe 0.35μm混波器模擬與量測結果 48
3.5.1 模擬結果 48
3.5.2 量測考量 50
3.5.3 量測結果 51
3.6 應用雙頻帶CMOS 0.18μm混波器模擬與量測結果 55
3.6.1 模擬結果 55
3.6.2 量測考量 58
3.6.3 量測結果 58
3.7 應用雙頻帶混波器結果討論 62
第四章 雙頻帶直接降頻系統接收機 63
4.1系統簡介 63
4.1.1 簡介 63
4.1.2 靈敏度 64
4.1.3 動態範圍 64
4.2 前端接收機架構剖析 65
4.3 應用雙頻接收機電路分析與設計 66
4.3.1 系統架構分析 66
4.3.2 主動分波器 67
4.3.3 混波器 68
4.3.4 接收機整合 69
4.4 應用雙頻帶接收機電路佈局圖 70
4.5 應用雙頻帶接收機模擬結果 70
4.5.1 主動巴倫模擬結果 70
4.5.2 接收機模擬結果 72
4.6 應用雙頻帶接收機結果討論 76
第五章 UWB 雜訊抵消技巧之低雜訊放大器 77
5.1 UWB低雜訊放大器 77
5.2 雜訊抵消技巧原理 78
5.3 雜訊抵消低雜訊放大器架構 78
5.4 晶片攝影圖 80
5.5 模擬結果 80
5.6 量測結果 81
5.7 討論 85
第六章 結論 87
參考文獻 89


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