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研究生:游翔鉦
研究生(外文):Hsiang-Cheng Yu
論文名稱:應用於H.264/AVC之高輸出率CAVLC編碼器架構設計與實現
論文名稱(外文):Design and Implementation of High Throughput CAVLC Encoder for H.264/AVC
指導教授:范志鵬范志鵬引用關係
指導教授(外文):Chih-Peng Fan
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:56
中文關鍵詞:高輸出率CAVLC編碼
外文關鍵詞:CAVLC
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近年來人們對影像畫質的要求越來越高,造就視訊壓縮的技術越來越進步,因為要符合即時處理高畫質影像的設計,不得不對視訊壓縮技術做改良,而H.264壓縮技術就是目前的主流。然而在H.264的CAVLC編解碼端控制了最主要的位元輸出,為了達到即時輸出高畫質影像的位元串,CAVLC的編解碼就必須更快以達到即時處理高畫質影像的要求。

本論文就CAVLC編碼端做改良設計,提出一個應用於H.264/AVC之高輸出率CAVLC編碼器架構設計與實現。本架構採取了不同方塊(4x4與2x2)間的平行處理,同時相同的方塊做管線處理,減少了編碼時間並提升了輸出速度; 另外在方塊內部的係數編碼,我們也採取平行處理(Level與Run_Before)的方式,提升了編碼一個方塊的速度,並且利用前級提供的方塊資訊,有效的跳過全零方塊,而在CAVLC內部各個編碼器的地方,我們也採取了化簡LUT的方法,使得硬體面積能夠下降,最後再設計一個位元串封包器,將各個編碼器輸出的位元串整合送出。

本論文提出的架構,是為了達到高畫質影像即時輸出而設計,並且在不改變CAVLC標準下將其架構改良,最後透過Cell-based流程驗證我們設計的硬體架構。VLSI實作結果顯示,我們所提出的架構能夠達到每秒處理1.76x10^6個MB,超過了HD1080p所要求的即時處理速度。


In recent years, because peoples have required more and more high quality video on displayers, it results in the technology of video compression to be more progressive. In order to match the high quality video for the real-time applications, we must enhance the video compression technology, and the H.264 compression technique is one of the selected topics for video compressions. In the H.264 encoding system, the CAVLC is the unit which controls the bit stream output. To achieve real-time and high-quality video outputs, the CAVLC coding system should be quicker to achieve the high quality video demand because the high quality video have a lot of messages to be encoded.

In the thesis, we make the improvement design on the CAVLC encoder side, and finish the implementation of the high throughput CAVLC encoder for H.264/AVC. The proposed architecture uses the parallel processing scheme for the different block sizes, i.e. 4x4 and 2x2 blocks, and it also uses the pipelined design at the same time to reduce the encoding clock cycles and increase the throughput. Furthermore, we use the parallel processing scheme in Level and Run_Before encoders to increase the encoding speed per block, and use the information which is obtained in the previous level to skip the zero blocks. In the CAVLC encoding system, we also use the look-up-table merge technique to reduce the sizes of the look-up tables, and it can decrease the required chip area. Finally, we design a bit stream packer to package the streams for the output.

The proposed architecture is designed to export the high-quality video stream immediately without changing the CAVLC standard in H.264/AVC, and we use the cell-based design flow to prove our hardware design. With TSMC 0.18

誌謝 I
中文摘要 II
英文摘要 III
目錄 IV
表目錄 VI
圖目錄 VII
第一章 緒論 1
1.1 前言 1
1.2 壓縮與編碼技術 1
1.3 動機與目的 2
1.4 論文架構 2
第二章 H.264/AVC視訊壓縮標準 3
2.1 H.264簡介 3
2.2 H.264編碼系統 7
2.3 CAVLC編碼簡介 8
2.3.1 Coeff_Token 11
2.3.2 TrailingOne 12
2.3.3 Level 12
2.3.4 Total_zeros 14
2.3.5 Run_Before 15
2.3.6 Encoding Example 15
第三章 文獻回顧 17
第四章 高輸出率的CAVLC 編碼架構 23
4.1 Observations 23
4.2 Block pipeline and parallel processing 25
4.3 Level and Run_Before encoder parallel processing 29
4.4 Coeff_token 36
4.5 Level encoder 38
4.6 Total zero encoder 42
4.7 Run encoder 45
4.8 Bitstream packer 47
第五章 模擬結果與比較 48
5.1 數據比較 50
第六章 結論 53
參考文獻 54

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