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研究生:葉宗祐
研究生(外文):Tsung-Yu Yeh
論文名稱:在無線感測器網路上設計與實做一個適用於不具備記憶體管理機制的硬體錯誤偵測方法
論文名稱(外文):A Hardware Fault Detection Scheme for MMU-less Embedded Processors in Wireless Sensor Networks
指導教授:張軒彬張軒彬引用關係
指導教授(外文):Hsung-Pin Chang
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊網路多媒體研究所
學門:電算機學門
學類:軟體發展學類
論文種類:學術論文
論文出版年:2009
畢業學年度:98
語文別:中文
論文頁數:78
中文關鍵詞:容錯感測器網路錯誤偵測
外文關鍵詞:fault tolerancesensor networkfault detection
相關次數:
  • 被引用被引用:1
  • 點閱點閱:187
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  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
基於成本、低耗電與體積小的設計考量,感測節點的硬體架構通常較為簡化,例如並不具備記憶體管理系統及hardware trap來輔助系統偵測錯誤。
有鑑於此,我們提出雙節點架構,備用的節點可以在主用節點失效時取而代之。首先,在處理器與記憶體的錯誤偵測上,我們提出軟體方式來實做並模擬fatal hardware trap,彌補主用節點先天硬體上的不足,此外,因為錯誤可能是暫時性或永久性,當主用節點捕捉到硬體錯誤時,可請求備用節點一同重新執行(parallel re-execution)以診斷硬體錯誤是暫時性或永久性。其次,對於不影響系統可用性的錯誤,如感測裝置的損壞,主用節點利用錯誤資料模型來偵測感測資料是否發生錯誤,如果錯誤,則請求備用節點啟動感測並回傳資料,取代主用節點上的錯誤資料。
實驗結果顯示,我們提出的雙節點架構有很好的處理器錯誤偵測率及感測資料錯誤更正率,另外我們也測量了處理器與記憶體的硬體錯誤偵測延遲(fault detection latency),並且討論錯誤偵測延遲的數據如何影響我們雙節點架構上的檢查點策略(checkpointing)。
The architecture of embedded sensor is always designed for the purpose of low-energy consumption, low cost, and small size. As a result, this resource-constraint platform does not contain memory protection unit(MMU) and a variety of fatal hardware traps.
To overcome this difficulty, we propose a dual-node architecture in which the backup node can replace the primary node who failed. First of all, we simulate fatal hardware trap to detect faults of processor and memory; Later, primary node requests the backup node to re-execute simultaneously. Based on the outcome of the parallel re-execution, faults can be categorized into transient faults or permanent faults. Secondly, for those faults which do not affect the system’s availability, like faults of sensing I/O device, primary node can detect it with sensing data fault model and request backup node to re-sense in order for correction.
Finally, the evaluation shows that our dual-node architecture has good fault coverage of processor and I/O sensing data. We also measure the fault detection latency and discuss about how the latency affects the checkpoint policy of the proposed dual-node architecture.
第一章 緒論 1
1.1簡介 1
1.2動機 2
1.3貢獻 3
1.4論文架構 5
第二章 相關工作 7
2.1 Monitoring of Sensing Data 7
2.2 Sensor Network Data Fault Types 8
2.3 Processor Fault Tolerance 11
2.4 Rx ~ A Safe Method to Survive Software Failures 12
2.4.1 Concurrency Bug and Memory Related Bug 12
2.4.2 Re-execution with changed environment 12
2.4.3 Multiple Checkpoints 13
2.5 Hang Symptom-Based Detection 13
2.5.1 Hang異常症狀 13
2.5.2 Hang異常徵狀的偵測方法比較 15
2.6 SWAT : Symptom-Based Fault Detection 16
2.7 Sensor Operating System : SOS 18
2.7.1簡介 18
2.7.2硬體平台 18
2.7.3動態的應用程式模組 19
2.7.4應用程式模組的溝通 21
2.7.5模組執行的排程 23
第三章 系統設計與實作 25
3.1系統架構 25
3.2硬體偵錯的設計 27
3.2.1電池,uart channel,節點系統性損壞,無線電晶片 27
3.2.2感測I/O裝置 29
3.2.3處理器與記憶體 32
3.2.3.1基於軟體異常症狀的偵錯方式 32
3.2.3.2 Data access trap 33
3.2.3.3 Memory management error trap 38
3.2.3.4 RED state trap 39
3.2.3.5 App abnormal exit 40
3.2.3.6 Watchdog timer reset trap 40
3.2.3.7 Heart beat message trap 42
3.2.3.8 System timer trap 44
3.3處理器與記憶體錯誤的診斷 – 永久性錯誤或暫時性錯誤 47
第四章 實驗結果 53
4.1實驗環境 53
4.2 Sensor data fault injection 53
4.3 Processor and memory fault injection 57
4.3.1暫存器與加法器的錯誤偵測 61
4.3.2 SRAM的錯誤偵測 64
4.3.3 Program memory的錯誤偵測 66
4.4執行負擔 67
4.5能源消耗負擔 73
第五章 結論及未來工作 75
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