臺灣博碩士論文加值系統

由於國內故障分析技術之研究並不多，所以本論文主要是建立一個完整的故障分析流程，深入探討互補式金氧半導體在奈米製程故障分析上所遇到的挑戰。首先探討各個故障點的定位技術、優缺點以及舉實例來加以說明。故障點分析的技術有液晶熱反應偵測術 (liquid crystal microscopy) 、微光偵測術 (photon emission microscopy) 、熱光束產生電阻變化偵測術 (optical beam induced resistance change) 和靜態隨機儲存記憶體利用測試模組的故障點分析 (static random access memory of bitmap programming) ，由於奈米製程積體電路的物理上的限制，使的故障點的定位變的非常的困難，針對奈米製程故障點定位，另外探討一個新的技術，互補式金氧半導體積體邏輯電路利用測試模組的故障點分析 (diagnosis) ，最後針對各故障點定位技術做一個比較。
接下來簡單探討幾種故障分析樣品處理的方法，有研磨法、聚焦離子束電路修改法 (focused Ion beam circuit repair) 、濕蝕刻、乾蝕刻等，研究其在奈米製程上故障分析遇到的挑戰。另外探討物性上樣品檢視的幾種工具如光學顯微鏡 (optical microscope) 、掃描式電子顯微鏡 (scanning electron microscope) 、聚焦離子束切割 (focused Ion beam X-section) 、穿透式電子顯微鏡 (transmission electron microscope) 、掃描穿透式電子顯微鏡 (scanning transmission electron microscope) 、能量散佈X光譜儀 (Energy Dispersive Spectroscopy) ，接下來是電性上樣品檢視的幾種工具如掃描式電容量測 (scanning capacitor microscopy) 、被動式電壓對比 (passive voltage contrast) 等。最後是因應奈米製程在電性上樣品檢測的兩個新的技術與應用，一個是傳導式原子力量測 (conductive atom force microscopy) ，研究如何偵測出金氧半導體氧化層的缺陷，研究如何偵測出連接導線高阻值的問題，最後是奈米探針量測 (nano-probing) 的技術，兩個實例應用研究如何偵測出金氧半導體源極到汲極線缺陷的問題，並討論其機制。

The study of failure analysis (FA) is rare internal. Thus the purpose of this thesis is to setup a complete FA flow and to study the challenges of couple metal oxide semiconductor (CMOS) FA in nano process. First to study each technique of failure site localization, advantages, disadvantages and limitations and illustrated by real cases. The techniques of failure site localization are liquid crystal microscopy, photon emission microscopy, optical beam induced resistance change and static random access memory of bitmap programming. Because of the physical limitation of nano process integrated circuit (IC), failure site localization becomes more and more difficult. To study a new technique which is FA of CMOS logic IC by testing pattern, called diagnosis.
Next, simply introduces several methods of FA of sample preparation as top lapping, focused Ion beam (FIB) circuit repair, wet etching and dry etching and discusses the challenges of FA in nano process. Then simply introduces several methods of sample inspection analysis in physically as optical microscope, scanning electron microscope, FIB X-section, transmission electron microscope, scanning transmission electron microscope and energy dispersive spectroscopy and in electrically as scanning capacitor microscopy and passive voltage contrast. Finally, two new techniques and applications of sample inspection analysis in electrically in order to analysis more accurate in nano process, one is conductive atom force microscopy, to study CMOS gate oxide defect localization and inter connection high resistance detection. Another is nano-probing technique, to study two real cases of applications of source to drain dislocation detection and discusses their mechanisms.

Content
Abstract (in Chinese) I
Abstract (in English) III
Acknowledgement V
Contents VI
Table Captions IX
Figure Captions X

CHAPTER 1 Introduction 1
1-1. Process Proceeding 1
1-2. Failure Analysis Flow 2
CHAPTER 2 Failure Site Localization 7
2-1. Liquid Crystal Microscopy 7
2-1-1. Theory and System Setup 7
2-1-2. Case Study 8
2-1-3. Advantage and Disadvantage 8
2-2. Photon Emission Microscopy 9
2-2-1. Theory and System Setup 9
2-2-2. Case Study 10
2-2-3. Advantage and Disadvantage 10
2-3. Optical Beam Induce Resistance Change 11
2-3-1. Theory and System Setup 11
2-3-2. Case Study 13
2-3-3. Advantage and Disadvantage 13
2-4. Bitmap 14
2-4-1. Theory and System Setup 14
2-4-2. Case Study 14
2-4-3. Advantage and Disadvantage 15
2-5. Diagnosis 16
2-5-1. Theory and System Setup 16
2-5-2. Case Study 16
2-5-3. Advantage and Disadvantage 17
2-6. Comparison 17
CHAPTER 3 Challenges of Sample Preparation and Inspection Analysis 36
3-1. Sample Preparation 36
3-1-1. Lapping 36
3-1-2. Focused Ion Beam Circuit Repair 37
3-1-3. Wet Etching 37
3-1-4. Dry Etching 38
3-2. Physical Inspection Analysis 39
3-2-1. Optical Microscope 39
3-2-2. Scanning Electron Microscope 40
3-2-3. Focused Ion Beam X-section 41
3-2-4. Transmission Electron Microscope 41
3-2-5. STEM/EDS 42
3-3. Electrical Inspection Analysis 43
3-3-1. Scanning Capacitor Microscopy 43
3-3-2. Passive Voltage Contrast 44
CHAPTER 4 Applications of New Electrical Inspection Analysis 57
4-1. Conductive Atom Force Microscopy 57
4-1-1. System 58
4-1-2. Application I: Gate Oxide Defect Localization 58
4-1-3. Application II: Inter Connection High Resistance Detection 59
4-1-4. Advantage and Disadvantage 60
4-2. Nano-probing 61
4-2-1. System 62
4-2-2. Application I: Specific Source to Drain Dislocation Detection 63
4-2-3. Application II: Specific Source to Drain Dislocation Detection 64
4-2-4. Advantage and Disadvantage 65
4-3. Comparison 66
CHAPTER 5 Conclusion and Future Work 83
5-1. Conclusion 83
5-2. Future Work 83
Reference 86

[1] Texas Instruments, “The Chip that Jack Built, (HTML), accessed May 29, (2008).
[2] Moore, Gordon E., Cramming more components onto integrated circuits, (1965).
[3] Wgsimon, “CPU Transistor Counts and Moore’s Law, (HTML), accessed December 29, (2008).
[4] Morris Chang, “IC ‘megatrends’ point to post-Moore’s Law era, speech at the Taiwan+China Semiconductor Outlook Conference in San Joe, Sept. 15, (2003).
[5] Taiwan Semiconductor Manufacturing Company, “2008 Business Overview, pp. 8, (2008).
[6] De Gennes, P.G. and Prost, J, “The Physics of Liquid Crystals, Oxford: Clarendon Press., (1993).
[7] Chandrasekhar, S., “Liquid Crystals, Cambridge: Cambridge University Press., (1992).
[8] H.C. Huang, “The Comparison of Failure Analysis Technologies in Complementary Metal Oxide Semiconductor Integrated Circuit, Adv. Master., pp. 10, (2006).
[9] A. Csendes, V. Sz?kely, M. Kerecsen-Rencz, “Thermal mapping with liquid crystal method, Microelectronic Engineering, V.31, pp.281-290 (1996).
[10] Christian Boit, “Fundamentals of photon emission(PEM) in silicon – electroluminesence for analysis of electronic circuit and device functionality, Microelectronics Failure Analysis Desk Reference 5th Edition, pp. 357-369.
[11] S. Sze, “Physics of Semiconductor Devices, John Wiley and Sons, New York, (1981).
[12] Donald A. Neamen, “Semiconductor Physics ＆ Devices, McGraw Hill, Third Edition, Dec., (2002).
[13] B. Marchand, D. Blachier, C. Leroux, G. Ghibaydo, F. Balestra, G. Reimbold, “Generation of Hot Carries by Secondary Impact Ionization in Deep Submicron Devices: Model and Light Emission Characteristics, IEEE 38th Annual International Reliability Physics Symposium, San Jose, California, pp. 93-97, (2000).
[14] Bram Kruseman, Martijn Goossens, Victor Zieren, “Photon Emission Microscopy in 90nm CMOS Technologies, 30th ISTFA, pp. 210-215, Nov., (2004).
[15] Daniel L. Barton, Edward I. Cole Jr., Karoline Berhard-Hofer, “Flip-Chip and Backside Sample Preparation Techniques“, Microelectronics Failure Analysis, pp. 43 –49, Oct., (2004).
[16] J. Colvin, “BGA and advanced package Wire to Wire bonding for Backside emission microscopy, International Symposium Testing and Failure Analysis proceedings, pp.365-375, (1999).
[17] C.H. Wang, S.W. Lai, Z.H. Lee, J.H. Chou, “The Enhancement of Abnormal Photon Emission Identification for Advanced Processes using a Backside Cooling PEM System, 31th ISTFA, pp. 241-244, (2005).
[18] Hamamatsu Inc., Phemos Series General Catalogue, (HTML), pp. 6, (2009).
[19] Nikawa, K; Tozaki, S, Principles Novel OBIC Observation Method for Detecting Defects in Al Stripes Under Current Stressing, Proceedings of the 19th International Symposium for Testing and Failure Analysis (Materials Park, Ohio: ASM International), pp. 303–310, (1993).
[20] Cole, E. I; Tangyunyong, P; Barton, D.L, Backside Localization of Open and Shorted IC Interconnections, 36th Annual International Reliability Physics Symposium (The Electron Device Society and the Reliability Society of the Institute of Electrical and Electronics Engineers, Inc.), pp. 129–136, (1998).
[21] Thomas Johann Seebeck (1770-1831), ERIC Weisstein’s World of Biography, Wolfram Research, http://scienceworld.wolfram.com
[22] Falk, R.A, Advanced LIVA/TIVA Techniques, Proceedings of the 27th International Symposium for Testing and Failure Analysis (Materials Park, Ohio: ASM International), pp. 59–65, (2001).
[23] Michael R. Bruce, Victoria J. Bruce, David H. Eppes, Jacob Wilcox, “Soft defect localization (SDL), ISTFA, p21-27, (2002).
[24] B F Hann, “An approach to Electrical Conductivity in Solids, Physics Education, IOP Electronic Journals, pp.207-211, (1969).
[25] Hamamatsu Inc., uAMOS-200 Catalogue, (HTML), pp. 2, (2009).
[26] K. Nikawa, S. Inoue, “Various Contrasts Identifiable from the Backside of a Chip by 1.3um Laser, ISTFA, pp. 387-392, (1996).
[27] S. J. Bennett, “The thermal expansion of copper between 300 and 700K, Journal Physics D: Applied Physics 11 pp. 777-780, (1978).
[28] David Hodges, Horace Jackson, Resve Saleh, “Analysis and Design of Digital Integrated Circuits, McGraw Hill published, 3rd edition, pp. 359-361, July, (2003).
[29] Kinoshata, K., Saluja, “Built-in Testing of Memory using on-chip compact testing scheme, Proc. Of IEEE International Test Conference, (1984).
[30] C. Brillert, C. Burmer, P. Egger, “SRAM Failure Analysis Flow. 27th ISTFA, (2001).
[31] P. Egger, C. Burmer, “SRAM Failure Analysis Strategy, 29th ISTFA, Nov., (2003).
[32] J.-Y. Glacet, F. Lee, “Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement, 26th ISTFA, (2000).
[33] Montgomery Phister, “Logical Design of Digital Computers, Wiley., pp. 128, (1958).
[34] J.B. Khare, W. Maly, S. Griep, D. Schmitt-Landsiedel, “Yield-oriented computer-aided defect diagnosis, IEEE Trans. On Semi. Manufacturing, Vol. 8, Issue 2, pp. 195-206, May, (1995).
[35] C. Hora, R Segersm S. Eichenberger, M, Lousberg, “An Effective Diagnosis Method to Support Yield Improvement, Proc. Intl. Test Conf., (2002).
[36] W. May, A. Gattiker, T. Zanon, T. Vogels, R.D. Blanton, T. Storey, “Deformation of IC Structure in Test and Yield learning, Proc. Intl. Test Conf., pp. 856-865, (2003).
[37] D. Appello, A. Fudoli, V. Tancorre, “Understanding Yield Losses in Logic Circuits, IEEE Design and Test of Computers, Vol.21, No.3, pp. 208-215, May-June, (2004).
[38] A. Leininger, P. Muhmenthaler, W.T. Cheng, N. Tamarapalli, W. Yang, H. Tsai, “Compression Mode Diagnosis Enables High Volume Monitoring Diagnosis Flow, ITC, Paper 7.3, (2005).
[39] Jayanth Mekkoth, Murali Krishna, Jun Qian, “Yield Learning with Layout-aware Advanced Scan Diagnosis, 32th ISTFA, (2006).
[40] J. Waicukauski, E. Lindbloom, “Failure Diagnosis of Structured Circuits, IEEE Design and Test of Computer, Vol. 6, No.4, pp. 49-60, (1989).
[41] H. Balachandran, J. Parker, D. Shupp, K. Butler, C. Force, J. Smith, “Correlation of logical failures to a suspect process step, Proc. Intl. Test Conf., pp. 458-466, (1999).
[42] A. Kinra, H. Balachandran, R. Thomas, J. Carulli, “Logic mapping on a microprocessor, Proc. Intl. Test Conf., pp. 701-710, (2000).
[43] R. D. Blanton, “Failure Diagnosis using Fault Tuples, Proc. Of IEEE Latin American Test Workshop, pp. 253-257, (2001).
[44] T. Bartenstein, D. Heaberlin, L. Huisman, D. Sliwinki, “Diagnosis Combinational Login Designs using the Single Location At-A-Time (SLAT) Paradigm, Proc. Intl. Test Conf., pp. 287-296, (2001).
[45] W.-T. Cheng, K.-H. Tsai, Y. Huang, N. Tamarapalli, J. Rajski, “Computer independent direct diagnosis, Proc. Of Asian Test Symp., pp. 15-17, (2004).
[46] D. Bodoh, A. Blakely, T. Garyet, “Diagnostic Fault Simulation for the Failure Analysis, Proc. Intl. Symp. For Test and Failure Analysis, (2004).
[47] R. Desineni, R.D. Blaton, “Diagnosis of Arbitrary Defects using Neighborhood Function Extraction, Proc. Of VLSI Test Symp., (2005).
[48] C. Eddleman, N. Tamarapalli, W.-T. Cheng, “Advanced Scan Diagnosis based Fault Isolation and Defect Identification for Yield Learning, Proc. Of ISTFA, (2005).
[49] C. Smith, K Symond, “Novel Deprocessing Techniques to Analyze Gate Level Defects, ISTFA, pp. 275-278, (1995).
[50] Katarina Logg., “Optical Microscopy, Chalmers Dept. Applied Physics, pp. 4, (2006).
[51] Hitachi High Technologies America, Inc., “S-5500 In-Lens FE SEM, (HTML), accessed (2009).
[52] V. Castaldo, C.W. Hagen, B. Rieger and P. Kruit, “Sputtering limits versus signal-to-noise limits in the observation of Sn balls in a Ga+ microscope J. Vac. Sci. Tech. B26, p. 2107, (2008).
[53] J. Orloff, L.W. Swanson and M. Utlaut, “Fundamental Limits on Imaging Resolution in Focused ion Beam Systems, J. Vac. Sci. Tech. B14, p. 3759, (1996).
[54] Carter, C. B., Transmission Electron Microscopy, 1 - Basics. Plenum Press., (1996).
[55] Jon C. Lee, B.H. Lee, “The Versatile Application for In-situ Lift-out TEM Sample Preparation by Micromanipulator and Nanomotor, ISTFA, (2005).
[56] Crewe, Albert V, Isaacson, M. ＆ Johnson, D., A Simple Scanning Electron Microscope, Rev. Sci. Inst. 40: 241–246., (1969).
[57] Digital Instrument Veeco Metrology, “Scanning Capacitor Microscopy (SCM), Support Note No. 289, Rev. A, pp. 289-7, (2000).
[58] Natasja Duhayon, “Experiment study and optimization of scanning capacitance microscopy for two-dimensional carrier profiling of submicron semiconductor device, thesis of PhD, June, (2006).
[59] James R.Beall, “Voltage Contrast Techniques and Procedures, Microelectronic Failure Analysis Desk Reference 3rd Edition, pp. 153-161. (1997).
[60] David P. Vallett., IC Failure Analysis: The Importance of Test and Diagnostics, IEEE Design and Test of Computers, vol. 14, no. 3, pp. 76-82, July-September, (1997).
[61] H. Seiler, “Secondary Electron Emission in the Scanning Electron Microscope, Journal of Applied Physics, 54, pp. R1-R8, (1983).
[62] Newbury, D.E., Joy, D.C., Echlin, P., Fiori, C.E., and Goldstein, J.I., “Advanced Scanning Electron Microscopy and X-Ray Microanalysis, Plenum, New York, (1986).
[63] H.C. Huang, “The Comparison of Failure Analysis Technologies in Complementary Metal Oxide Semiconductor Integrated Circuit, Adv. Master., pp. 70, (2006).
[64] R. Rosenkranz, “FIB assisted localization and preparation of gate oxide fails, EFUG, (2002).
[65] A.N. Campbell, J.M. Soden, “Voltage Contrast in the FIB as a Failure Analysis Tool, Microelectronic Failure Analysis Desk Reference 4th Edition, pp. 161-167, (1999).
[66] G. Binnig, H. Rohrer, “Scanning tunneling microscopy, IBM Journal of Research and Development, (1986).
[67] Jon C. Lee and J. H. Chuang, “Fault localization in contact level by using conductive atomic force microscopy, 29th International Symposium for Testing and Failure Analysis, (2003).
[68] C. Smith, K Symond, “Novel Deprocessing Techniques to Analyze Gate Level Defects, ISTFA, pp. 275-278, (1995).
[69] Cheng-Piao Lin, Cheng-Hsu Wu and Cheng-Chun Ting, “A novel electrical test by C-AFM to differentiate gate-to-SD gate oxide short from non-gate oxide short defect in real products, 30th ISTFA, (2004).
[70] Z.H. Lee, C.J. Lin, S.W. Lai and J.H. Chou, “Gate Oxide Defect Localization and Analysis by Using Conductive Atomic Force Microscopy, 31th ISTFA, pp. 235-238, (2005).
[71] Thong, J., Electron Beam Probing. Microelectronics Failure Analysis. ASM International. pp. 438–443, (2004).
[72] Kolachina, S., Introduction to Laser Voltage Probing (LVP) of Integrated Circuits. Microelectronics Failure Analysis. ASM International. pp. 426–430, (2004).
[73] Desplats, R.; Eral, A.; Beaudoin, F.; Perdu, P.; Chion, A.; Shah, K.; Lundquist, T., IC Diagnostic with Time Resolved Photon Emission and CAD Auto-channeling. Proceedings from the 29th International Symposium for Testing and Failure Analysis. Materials Park, Ohio: ASM International. pp. 45–54, (2003).
[74] R. Rosenkranz, S. D?ring, W. Werner, L. Bartholom?us and S. Eckl, “Active Voltage Contrast for Failure Localization in Test Structures, ASM International, (2006).
[75] Multiprobe, Inc., “PicoCurrent imaging using the Multiscan Atomic Force Probe, (HTML), (2007).
[76] Frank siegelin, Anton Stuffer, “Dislocation related leakage in advanced CMOS devices, 31th ISTFA, pp. 59-63, Nov., (2005).
[77] C.H. Wang, C.M. Shen, C.J. Lin, Z.H. Lee, J.H. Chou, “the study and methodology of defects isolation for contacts of non-isolated active regions on new logic designs, 31th ISTFA, pp. 479-483, Nov., (2005).
[78] S.C. Liou, J.H. Chuang, J.C. Lee, “The physical failure analysis of Iddq and Iddq fail in 90nm logic products, 12th IPFA, pp. 47-51, (2005).
[79] C.H. Wang, S.W. Lai, C.Y. Wu, B.T. Chen, J.Y. Chiou, J.H. Chou, “The failure analysis of specific source-to-drain dislocation and case study, 34th ISTFA, pp. 245-248, Nov., (2008).
[80] Nathan Wang, Susan Li, “Application of 3-D Transmission Electron Microscopy in Semiconductor Device Analysis, EDFA, (2008).
[81] S.J. Cho, T.E. Kim, J.K. Hong, J.T. Hong, H.S. Kim, Y.W. Han, S.D. Kwon, Y.S. Oh, Logic Failure Analysis 65/45nm Device Using RCI ＆ Nano Scale Probe , China, 16th IPFA (2009).
[82] K. Mizukoshi, T. Oyamada, A. Shimase, Y. Matsumoto, S. Yorisaki and T. Majima, Fault Localization Using Electron Beam Current Absorbed in LSI Interconnects, Proc The 2004 International Meeting for Future of Electron Devices, Kansai, Kyoto, JAPAN, pp.391-392, (2004).