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研究生:林煜凱
研究生(外文):Yu-KaiLin
論文名稱:支援多重標準移動補償架構設計
論文名稱(外文):Architecture Design for Multi-Standard Motion Compensation
指導教授:謝明得謝明得引用關係
指導教授(外文):Ming-Der Shieh
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:53
中文關鍵詞:移動補償壓縮多重標準H.264VC-1AVSMPEG-2
外文關鍵詞:Motion CompensationCompressionMulti-standard
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影像壓縮技術越來越重要,各種視訊壓縮標準如MPEG-2、H.264/AVC、VC-1及AVS已相繼被提出,且目前的消費性產品大多支援多格式視訊解碼。雖可針對各項標準設計相對應之電路並於設計完成後加以整合,但此法亦會導致成本過高以及使用率過低之問題。本論文欲開發一支援H.264、MPEG-2、VC-1及AVS之移動補償(motion compensation)電路。
雖然不同標準中之移動補償所需之內插補點(interpolation)的運算方式皆是有限脈衝響應濾波器(finite impulse response filter),然而不同標準間之有限脈衝響應濾波器所擁有的係數、階數(tap),以及各個標準所之需之區塊大小(block size)以及內插補點之順序皆不同,故並非可直接引入心臟收縮式陣列(systolic array)的設計準則。為解決此問題,本論文於設計初期考量各個標準內插補點所需之係數、階數(tap)以及區塊大小與資料相依性提供一支援多格式標準之資料相依圖(dependence graph),並根據應用需求給定合適之投影向量(projection vector)以及排程向量(scheduling vector)產出所需之運算單元陣列(PE array)。
此外,根據先前所得之運算單元陣列,於考量硬體使用率並符合及即時播放需求下,本論文將補償不同位置的內插補點之運算單元陣列進一步共用,並移除不需的資料路徑(data path)、權重係數乘法器以達到低成本之設計目的,同時於設計過程中解決陣列合併所可能發生的資料衝突(data conflict)問題。以Verilog HDL實現此架構的RTL程式碼,於TSMC 0.18 μm製程下,其工作頻率在108MHz可支援HD 1080p解晰度,而其合成電路面積為29K 邏輯閘(gate)。

Recently years, video compression technologies have received increasing attention. Many video compression standards such as MPEG-2, H.264/AVC, VC-1 and AVS have been proposed, therefore, many consumer digital products will support multi-standard video decoding. Alternatively we can design IPs independently for each standard and then combine them intuitively with little effort. However this may results in high hardware cost and low utilization. In this thesis we try to propose an architecture which supports multi-standard motion compensation interpolation (MCI), including MPEG-2, H.264/AVC, VC-1 and AVS.
Although the MCI in each standard is finite impulse response (FIR) filter, each FIR has different weighting and number of taps. Moreover, the block size and the order of interpolation in each standard are also different. That means the processing element (PE) array can not be easily derived using systolic array mapping. In this thesis, a dependence graph (DG) of multi-standard MCI is proposed while considering the difference of MCI in the four standards. Then given the projection vector and scheduling vector, the PE arrays can be derived according to the target application.
Moreover, we combined the derived PE arrays to improve the hardware utilization and remove the redundant data path and multipliers to minimize the hardware cost. We implement our circuit with Verilog, and then synthesize our design by using TSMC 0.18 ?m CMOS technology. The operating frequency of our design is 108 MHz with 29K gates and our circuit can real-timely decode video sequence under HD 1080p resolution.

摘要 i
ABSTRACT ii
誌謝 iv
目錄 v
圖目錄 viii
表目錄 x
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 2
第二章 背景知識介紹 3
2.1 國際影音壓縮標準簡介 3
2.2 多重標準格式之移動補償 5
2.2.1 MPEG-2 5
2.2.2 H.264 5
2.2.3 VC-1 8
2.2.4 AVS 11
2.3 目前相關研究綜述 11
2.4 心臟收縮式陣列簡介 13
2.4.1 基本介紹 13
2.4.2 映射參數(Mapping Parameter) 13
2.4.3 排程向量(Scheduling Vector)之選擇 14
第三章 移動補償之可重組化架構設計 18
3.1 MPEG-2、H.264、VC-1及AVS移動補償差異性之比較 18
3.1.1 權重係數及有限脈衝響應濾波器之階數 18
3.1.2 區塊尺寸(Block Size) 18
3.2 多重標準之相依圖設計 19
3.3 支援多標準移動補償之可重組運算單元陣列設計 26
3.3.1 映射參數之設計 26
3.3.2 支援多標準移動補償之可重組運算單元陣列 27
3.3.2.1 映射完成之電路 27
3.3.3 資料流(Dataflow) 31
3.3.3.1 MPEG-2 31
3.3.3.2 H.264 32
3.3.3.3 VC-1 34
3.3.3.4 AVS 34
3.3.3.5 總結 35
3.3.4 合併與改良 35
3.4 支援多標準移動補償之可重組運算單元設計 38
3.5 硬體電路面積成本最佳化 40
3.5.1 運算單元陣列中多餘的資料路徑(Redundant Data Path) 40
3.5.2 運算單元陣列中多餘的權重係數(Redundant Weighting Coefficient) 42
3.5.3 運算單元資料寬度(Data Width)分析 44
第四章 實驗結果與分析比較 45
4.1 驗證流程 45
4.2 硬體實現結果 46
4.3分析與比較 47
第五章 結論及未來研究方向 50
5.1 結論 50
5.2 未來研究方向 50
參考文獻 51

[1]ISO/IEC, “Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbits/s, ISO/IEC 1117-2: video, Nov. 1991.
[2]ITU-T/SG 16/VCEG, “Video codec test model long term number 8, Doc, VCEG-N10, July 2001.
[3]ISO/IEC, “Information technology-generic coding of moving pictures and associated audio information- part 2: video, Standard 13818-2, 1995.
[4]ISO/IEC, “Coding of audio-visual objects - part 2: visual, ISO/IEC 14496-2, Apr. 1999.
[5]J. V. Team, “Draft ITU-T recommendation and final draft international standard of joint video specification, ITU-T Rec. H.264 and ISO/IEC 14496-10 AVC, May 2003.
[6]L. Fan, S. Ma, and F. Wu, “Overview of AVS video standard, in Proc. IEEE Int. Conf. Multimedia Expo., pp. 423-426, 2004.
[7]SMPTE “Proposed SMPTE standard for television: VC-1 compressed video bitstream format and decoding process, SMPTE 421M, Aug. 2005.
[8]S. Z. Wang, T. A. Lin, T. M. Liu, and C. Y. Lee, “A new motion compensation design for H.264/AVC decoder, in Proc. IEEE Int. Symp. Circuits Syst., vol. 5 pp.4558-4561, May 2005.
[9]T. Y. Kuo, Y. K. Lin, and T. S. Chang, “A memory bandwidth optimized interpolator for motion compensation in the H.264 video decoding, in Proc. IEEE Asia Pacific Conf. Circuits Syst, pp. 1244-1247, 2006.
[10]T. D. Chuang, L. M. Chang, T. W. Chiu, Y. H. Chen, and L. G. Chen, “Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control, in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., pp. 2009-2012, 2009.
[11]C. Yang, S. Goto, and T. Ikenaga, “High performance VLSI architecture of fractional motion estimation in H.264 for HDTV, in Proc. IEEE Int. Symp. Circuits Syst., pp. 2605-2608, May 2006.
[12]J. Zheng, W. Gao, D. Wu, and D. Xie, “A novel VLSI architecture of motion compensation for multiple standards, IEEE Trans. Consum. Electron., vol. 54, no. 2, pp.687-694, May 2008.
[13]L. Lu, J. V. McCanny and S. Sezer, “Multi-standard sub-pixel interpolation architecture for video motion estimation, in Proc. IEEE Int. SOC Conf., pp. 229-232, 2008.
[14]L. Lu, J. V. McCanny and S. Sezer, “Subpixel interpolation architecture for multistandard video motion estimation, IEEE Trans. Circuits Syst. Video Technol., vol. 19, no. 12, pp. 1897-1901, Dec. 2009.
[15]T. C. Chen, Y. W. Huang, and L. G. Chen, “Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC, in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., pp. 9-12, May 2004.
[16]C.D. Chien, H.C. Chen, L.C. Huang, and J.I. Guo, “A low-power motion compensation IP core design for MPEG-1/2/4 video decoding, in Proc. IEEE Int. Symp. Circuits Syst., vol. 5, pp. 4542-4545, May 2005.
[17]C. Y. Tsai, T. C. Chen, T. W. Chen, and L. G. Chen, “Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder, in Proc. IEEE Int. Midwest Symp. Circuits Syst., pp. 1199-1202, Aug. 2005.
[18]S. Yang, L. Zhenyu, G. Satoshi, and I. Takeshi, “A VLSI architecture for motion compensation interpolation in H.264/AVC, in Proc. IEEE ASICON’05, pp. 262-265, Oct. 2005.
[19]C. D. Chien, H. C. Chen, L. C. Huang, and J. I. Guo, “A low-power motion compensation IP core design for MPEG-1/2/4 video decoding, in Proc. IEEE Int. Symp. Circuits Syst., pp. 4542-4545, May 2005.
[20]S. Z. Wang, “A flexible motion compensation memory organization for dual-standard video decoder, SI2 Lab., National Chiao-Tung University, June 2005.
[21]V. Lappalainen, A. Hallapuro, T. D. Hamalainen, “Complexity of optimized H.26L video decoder implementation, IEEE Trans. Circuits Syst. Video Technol., vol. 13, pp. 717-725, no. 17, July 2003.
[22]H. W. Feng, Z. G. Mao, J. X. Wang and D. F. Wang, “Design and implementation of motion compensation for MPEG-4 AS profile streaming video decoding,. In Proc. IEEE Int. ASIC Conf., vol.2, pp. 942-945, Oct. 2003
[23]S. H. Wang and W. H. Peng, Y. He, G. Y. Lin, C. Y Lin, S. C. Chang, C. N. Wang and T. Chiang, “A platform-based MPEG-4 advanced video coding (AVC) decoder with block level pipelining, in Proc. IEEE ICICS-PCM, pp. 51-55, Dec. 2003.
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