臺灣博碩士論文加值系統

本論文設計並實作異質性多核心架構嵌入式系統平台之行程溝通(IPC)機制，提供運行於異質性多核心平台之行程間一對稱式之傳遞訊息與交換資料之管道。運行於不同處理器核心之行程藉由本論文提供之行程溝通機制，能夠有效地相互通訊、分享資料與協調同步，使多核心架構下之系統資源能有效地被利用。
本論文設計之對稱式行程溝通機制以共享記憶體架構為基礎。設計之內容包含: 存取不同匯流排之間共享記憶體之基本資料分享功能、適合傳輸大量資料之直接記憶體存取(DMA)機制、使用硬體中斷信號之高效能訊息傳遞機制、訊息儲存與管理功能等，以充分利用系統平台之特徵。為滿足應用程式行程溝通之多樣化需求與提高行程溝通之效率，本論文之設計將訊息傳送與接收功能分為等待式(Blocking)與非等待式(Non-Blocking)兩種模式，並設計應用程式介面(API)，以便利應用程式開發。
本論文之設計實作於PAC Duo系統平台。PAC Duo是工業技術研究院所開發之異質性多處理器核心架構平台，其系統晶片包含一顆ARM處理器核心與兩顆高階DSP處理器核心(又稱PACDSP)。本論文中以ARM端運行Linux作業系統、PACDSP端分別運行μC/OS-II即時系統核心與資料流(Dataflow)系統核心為應用程式執行環境，實作嵌入系統核心之訊息傳遞模組與訊息管理模組、應用程式介面函式庫，並利用PAC Duo支援之硬體中斷機制實作基本訊息傳遞機制。經效能實測結果顯示本論文之行程溝通機制，可符合應用程式之需求，並兼顧即時與非即時系統之作業條件。



關鍵詞: 異質性多核心、對稱式行程溝通、共享記憶體、直接記憶體存取、訊息管理模組、PAC Duo

This thesis designs and implements a symmetric Inter-Process Communication (IPC) mechanism for embedded system platform of heterogeneous multi-core architecture. The goal is to provide a symmetric architecture for processes running on different processor cores to communicate and exchange data. With this symmetric IPC mechanism, processes are able to achieve effective communication, sharing data, co-operative execution and synchronization. The utilization of system resources thereby can be improved.
The symmetric IPC is designed with shared memory architecture as the basis. It is composed of the fundamental functions of sharing data through accessing shared memory modules connected by different buses, DMA mechanism suitable for transferring large data blocks, high performance message passing mechanism based on hardware interrupt support, and message management functions in order to make the best of the system capacity. In meeting the various requirements of inter-process communication and improving the efficiency, the functions of sending and receiving messages in blocking and non-blocking mode are supported by the design. To help application development, application program interfaces (API) of using this mechanism are also included in the design.
For evaluation purpose, the design of this symmetric IPC mechanism is implemented using PAC Duo as the embedded system platform. PAC Duo is heterogeneous multi-core system-on-chip (SOC) developed by Industrial Technology Research Institute (ITRI), which consists of one ARM processor and two advanced DSP processors (PACDSP). The implementation assumes that Linux operating system is running on the ARM side and, on the two PACDSPs, the real-time kernel ?C/OS-II and a dataflow kernel are running respectively. Function modules of message passing and management are embedded into system kernel and an API function library is provided for application development. The results of performance evaluation show that this symmetric IPC mechanism meets the requirements of application with either real-time or non-real-time conditions.

第1章 緒 論 1
1.1 研究背景 1
1.2 單晶片多核心處理器架構 3
1.3 行程溝通機制 4
1.4 研究動機與目的 5
1.5 章節規劃 6
第2章 相關研究 7
2.1 Linux作業系統之行程溝通機制 7
2.2 Windows作業系統之行程溝通機制 11
2.3 單晶片多核心處理器架構之行程溝通機制 12
2.3.1 同質性多核心處理器之行程溝通機制 13
2.3.2 異質性多核心處理器之行程溝通機制 14
2.4 實例探討 15
2.4.1 德州儀器公司DaVinci之行程溝通機制 15
2.4.2 Cell處理器之行程溝通機制 18
2.5 討論 22
第3章 行程溝通機制設計 24
3.1 行程溝通機制架構與組成 24
3.1.1 跨匯流排共享記憶體之資料傳輸 26
3.1.2 直接記憶體存取(DMA)之資料傳輸 26
3.1.3 硬體中斷之訊息傳遞機制 27
3.2 共享記憶體管理機制 29
3.3 行程溝通管理者 31
3.4 訊息佇列儲存管理機制 33
3.5 訊息傳遞程序 35
3.5.1 非等待式訊息傳遞(Non-Blocking Send) 36
3.5.2 等待式訊息傳遞(Blocking Send) 38
3.6 訊息接收程序 39
3.6.1 非等待式訊息接收(Non-Blocking Receive) 40
3.6.2 等待式訊息接收(Blocking Receive) 42
3.7 系統運作說明 42
第4章 行程溝通機制實作 44
4.1 實作環境 44
4.1.1 硬體介紹 44
4.1.2 軟體介紹 49
4.2 跨匯流排共享記憶體資料傳輸之實作 49
4.3 直接記憶體存取(DMA)資料傳輸之實作 52
4.4 訊息佇列儲存管理機制之實作 53
4.5 行程溝通管理者之實作 58
4.6 訊息傳遞實作 60
4.6.1非等待式訊息傳遞 60
4.6.2等待式訊息傳遞 62
4.7 訊息接收實作 65
4.7.1非等待式訊息接收 65
4.7.2等待式訊息接收 66
第5章 功能測試與效能分析 69
5.1 測試環境 69
5.2 功能性測試 69
5.2.1 匯流排共享記憶體之資料傳輸驗證 69
5.2.2 直接記憶體存取之資料傳輸驗證 71
5.2.3 多核心間行程溝通驗證 72
5.2.3.1 多核心作業系統訊息傳遞與接收驗證 72
5.2.3.2 共享記憶體管理機制驗證 75
5.3 系統效能分析 78
5.3.1 共享記憶體與直接記憶體存取資料傳輸之效能分析 78
5.3.2 訊息佇列儲存管理機制之效能分析 82
5.3.3 訊息傳遞與接收之效能分析 84
第6章 結論與展望 89
6.1 結論 89
6.2 展望 90
參考文獻 91
附錄 A 95
自述 107

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