臺灣博碩士論文加值系統

隨著多媒體、通訊系統與半導體製程的進步，行動式視訊裝置功能越來越強大，也造成有大量的資料需要傳送或儲存以及電池續航力的問題。然而有限的儲存元件、頻寬與電池容量的限制下，直接地限制了大部分行動式視訊裝置的應用，於是可以達成高品質及低儲存空間的高效率資料壓縮與解壓縮演算法是非常重要的。
我們提出一適合嵌入於行動式視訊裝置之有失真嵌入式壓縮器/解壓縮器來減少晶片與外部記憶體間所需的資料傳輸量，以達成減低頻寬使用、縮小對外部記憶體的空間需求以及降低能量消耗。
在我們提出的演算法中，是以位元平面截斷編碼(BPTC)與預先定義的位元平面(圖樣)所構成。在維持壓縮率為2的前提下，將一4x2的像素陣列，由64位元壓縮為32位元的封包。首先將一4x2陣列以位元平面截斷編碼找出起始平面，再根據我們設定的門檻來選擇使用圖樣比對編碼(PCC)或是一倍壓縮與二倍壓縮平均對剩下的位元平面作處理，最後封存編碼後之像數至外部記憶體。
我們提出的硬體架構可以在100 MHz的操作頻率下，支援每秒三十張的高解析度電視規格(HD 1080)以及150 MHz的操作頻率下，支援H.264/SVC規格下，雙層每秒三十張的HD720/HD1080。由於壓縮率固定為2倍，可輕易地轉換記憶體位址並支援動作補償單元(Motion Compensation)的亂數存取。壓縮一巨型區塊(Macro Block)需要32個週期，解壓縮一個巨型區塊(Macro Block)只需16個週期。對於記憶體的存取次數節省了將近50%，降低了相當可觀的能量耗損。

With the development of multimedia, communication system and semiconductor progress, the functions of mobile video applications are getting stronger and stronger, resulting in the problems on huge volume of data transmission, storage and battery endurance concerns. Under the constraints of limited storage components, bandwidth and battery capacity, most of the applications of mobile video devices are restricted. Therefore, the algorithm which can achieve high quality and little storage space with high efficiency of data coding and decoding is very important.
We propose a lossy embedded compressor/de-compressor which is suitable for embedding into mobile video devices to reduce the data transmission between chip and external memory, in order to reduce utilization of bandwidth, volume of external memory and power consumption.
In the proposed algorithm, we adopt Modified Bit Plane Truncation Coding (MBPTC) and Predefined Bit Planes (Patterns). Under the premise of compression ratio as 2, we compress one 4x2-pixel array from 64 bits to 32 bits into one packet. The Modified Bit Plane Truncation Coding (MBPTC) calculates the Start Plane (SP) of the 4x2-pixel array first. Then, selecting Patterns Comparison Coding (PCC) or 1x and 2x Average according to the coding threshold we setup to compress residual bit planes and last, packs the compressed pixels to external memory. The average PSNR loss of proposed algorithm is 5.98 dB.
The hardware architecture we proposed is able to support HD 1080@100 MHz of 30 frames per second for HDTV specification and HD 720/HD1080@150 MHz of 30 per frames second in double layers for H.264/SVC specification. Because the compression ratio is fixed as two, it is easy to re-map memory address and support random access of Motion Compensation (MC).
To compress a Macro Block takes 16 cycles while to decompress a Macro block takes only 16 cycles. It saves 48.7% of memory accesses on the average, leading to save considerable power consumption.

CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 2
CHAPTER 2 PREVIOUS WORKS 3
2.1 LOSSLESS COMPRESSION METHOD 3
2.2 LOSSY COMPRESSION METHOD 4
2.2.1 Transform-based Compression methods 4
2.2.2 Differential Pulse Code Modulation (DPCM) Compression 5
2.2.3 Block Truncation Coding (BTC) Compression 6
2.3 SUMMARY 12
CHAPTER 3 PROPOSED ALGORITHM 13
3.1 OVERVIEW 13
3.2 ALGORITHM OF EMBEDDED COMPRESSION 16
3.2.1 Fully Patterns Comparison Coding 17
3.2.2 Patterns Comparison and Average Coding 20
3.2.3 Patterns Comparison and Multi-MBPTC Coding 21
3.2.4 Reduced Patterns Comparison and Average Coding 23
3.2.5 Formula 26
3.3 SUMMARY 28
CHAPTER 4 PROPOSED ARCHITECTURE 32
4.1 ARCHITECTURE OF ENCODER 32
4.1.1 Architecture of Modified Bit Plane Truncated Coding Encoder 33
4.1.2 Architecture of the Reduced Patterns Comparison Coding 33
4.1.3 Overall Encoder Design 34
4.2 ARCHITECTURE OF DECODER 35
4.2.1 Data Rearrange 36
4.2.2 Overall Decoder Design 36
4.3 IMPLEMENTATION AND VERIFICATION 37
4.3.1 Implementation 37
4.3.2 Verification 38
CHAPTER 5 SYSTEM INTEGRATION 41
5.1 ADOPTED H.264 HARDWARE SYSTEM 41
5.2 ACCESS ANALYSIS 43
5.2.1 Write Access 48
5.2.2 Read Access 48
5.3 PROCESSING CYCLE ANALYSIS 51
5.3.1 Ratio of Access Reduction 52
5.3.2 Simulation Result on Power Consumption 53
CHAPTER 6 CONCLUSION AND FUTURE WORKS 56
6.1 CONCLUSION 56
6.2 FUTURE WORK 57

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