臺灣博碩士論文加值系統

NAND型快閃記憶體之小面積及低功耗使之成為現今最重要的非揮發性記憶元件之一。它快速的讀寫時間讓其非常適合成為次世代之大量儲存媒介。然而，NAND型快閃記憶體的輸出入介面之工作頻率限制了資料傳輸的頻寬。為了在此頻寬限制下得到更高的效能，新世代的NAND型快閃記憶體元件提供交錯以及雙面運行之指令。因此NAND型快閃記憶體控制器也必須擁有支援這些先進指令集之能力以使整體之系統效能提升。
在本篇論文中，我們提出一個高效能之NAND型快閃記憶體控制器。它主要使用了兩項技巧，包括平行化指令處理及使用雙面指令之定址模式。藉由這些技巧，我們可以盡可能地將指令間的平行度最大化並降低單一指令平均之執行時間以得到較好的效能。實驗結果顯示，我們所提出的快閃記憶體控制器相較於一般基本功能之控制器在各種讀寫之效能均可提升達18%以上。

NAND flash memory is one of the most important components in non-volatile storage media because of its small size and low power consumption. Its fast erase and program time has made NAND flash very suitable for the new generation mass-storage device. However, the I/O interface frequency of NAND flash has limited the bandwidth of data transfer. In order to achieve higher performance under this bandwidth limitation, NAND flash device provides interleaved and two-plane command sets. Therefore, NAND flash controller must have the ability to enhance the related functionality to improve the overall system performance.
In this thesis, we propose a high-performance NAND flash controller by utilizing the two techniques, including out-of-order execution with multi-die commands and the two-plane addressing mode. By these techniques, we can maximize the commands being executed in parallel and shorten the average execution time per instruction to achieve higher data access performance. The experimental results show that the proposed NAND flash controller can improve the data access performance for both read and program for at least 18% compared to a basic NAND flash controller.

中文摘要 i
English Abstract ii
誌謝 iii
Contents iv
Lists of Tables vi
Lists of Figures vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview of the proposed flash controller 2
1.3 Thesis organization 3
Chapter 2 Physical Properties of NAND Flash 4
2.1 Cell array organization 4
2.2 SLC VS. MLC 6
2.3 Operation principles 7
2.4 Basic NAND flash array 8
2.5 Advanced NAND flash array 10
Chapter 3 Functionalities of a Basic NAND Flash Controller 12
3.1 System architecture of NAND flash chip 12
3.2 The ONFi standard 13
3.3 Basic command management 14
3.4 Basic NAND flash interface controller 16
Chapter 4 Proposed NAND Flash Controller 17
4.1 Concept 17
4.2 Out-of-order execution 19
4.3 In-order commitment 22
4.4 Two-plane addressing mode 23
4.5 Interleaved command 25
4.6 Conclusions 27
Chapter 5 Experimental Results 28
5.1 Ideal Performance of commands 28
5.2 Experiment setup 30
5.3 EDA environment and synthesis result 31
5.4 NAND Flash simulation model 32
5.5 Experimental Results 32
Chapter 6 Conclusions and Future Works 36
References 37

參考文獻的頁碼應接續下去，而非另立新目[R-1]。


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