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研究生:謝忠穎
研究生(外文):Hsieh, Chung-Ying
論文名稱:可用於工作在次臨界/近臨界電壓區間綠色節能科技之製程、電壓、溫度高適應性超低電壓時脈系統設計
論文名稱(外文):Ultra-Low Voltage PVT-Robust Clock System Design for Sub/Near-Threshold Green Technologies
指導教授:黃威黃威引用關係
指導教授(外文):Hwang, Wei
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:93
中文關鍵詞:次臨界近臨界邏輯努力緩衝時脈樹時脈產生器製程變異電壓變異溫度變異
外文關鍵詞:sub-thresholdnear-threshollogical effortbuffered clock treeclock generatorprocess variationvoltage variationtemperature variation
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本論文提出一個可用於次臨界/近臨界電壓區間綠色節能科技之製程、電壓、溫度高適應性超低電壓時脈系統。針對可感知的電路設計,本論文提出了統一的邏輯努力模型,它已經建立在四個不同的CMOS 奈米世代和環境參數的變異,包括供應電壓從0.1 到1 伏和溫度從-50 到125 度。此模型的最多平均誤差不超過8.4%。
藉著使用統一的邏輯努力模型,一個溫度強健之緩衝時脈樹被提出,用於減輕溫度所造成的時脈相位差。邏輯努力-一個傳遞延遲的指標,跟隨著溫度與供應電壓變化,藉由可調寬度之緩衝器來控制。在這個設計裡面,溫度感測器測得不同部位的溫度並且動態調整相對應的緩衝器的邏輯努力,來減少脈衝相位差。
在UMC 65 奈米科技中,可調寬度之緩衝器與脈衝H 樹在佈局後模擬裡已被建立,它顯示了脈衝相位差可被減少最多到97.8%,平均72.2%。一個次臨界/近臨界可程式時脈產生器被提出,它可以產生1/8 到4 倍參考時脈頻率的輸出時脈。變異感知的邏輯設計在這個時脈產生器已被執行。脈衝循環結構的採用減少了製程變異所造成的輸出時脈抖動。此外,我們實現一個製程、電壓、溫度補償單位,用於調整時脈產生器的鎖定範圍。參考時脈的頻率在0.2伏是625 千赫茲,在0.5 伏是5 百萬赫茲。
This thesis proposes an ultra-low voltage (ULV) PVT-robust clock system for sub/near-threshold green technologies. For variation-aware circuit design, the unified logical effort models are proposed, which have been established over the four different nanoscale CMOS generations and environmental parameter variations with wide supply voltage 0.1~1V and temperature range -50~125ºC. The average modeling error is no more than 8.40%.
By using the unified logical effort models, a thermally robust buffered clock tree is proposed for mitigating the temperature-induced clock skew. Logical effort - an index of propagation delay, varying with thermal and supply voltage conditions, is controlled by a tunable-width buffer. In this design, the temperature sensor senses the
temperature of different parts of the clock tree and adjusts the logical effort of the corresponding clock buffers dynamically to reduce the clock skew. In UMC-65nm
technology, tunable-width buffers along with 7th-layer metal interconnect clock H-tree are constructed in post-layout simulation, which shows that the clock skew is reduced by up to 97.8%, and 72.2% in average.
A sub/near-threshold programmable clock generator is proposed, which is able to create output clock with frequency 1/8~4 times of the reference clock. The variation-aware logic design is performed in the clock generator. The adoption of pulse-circulating scheme reduces process induced output clock jitter. In addition, we realize a PVT compensation unit for adjusting the locking range of clock generator. The frequencies of reference clock are 625KHz at 0.2V and 5MHz at 0.5V.
Chapter 1 Introduction ................................................................................................ 1
1.1 Background .......................................................................................................... 1
1.2 Motivation ............................................................................................................ 2
1.3 Organization ......................................................................................................... 3
Chapter 2 Overview on Clock Distribution Networks and Clock Generator ........ 4
2.1 An Overview on Clock Distribution Networks [2.1] ........................................... 4
2.1.1 Synchronous Systems ................................................................................... 4
2.1.2 Theoretical Background of Clock Skew ....................................................... 6
2.1.3 Clock Distribution Design of Custom VLSI Circuits ................................... 7
2.1.3.1 Buffered Clock Distribution Trees ......................................................... 8
2.1.3.2 Symmetric H-Tree Distribution Networks ........................................... 10
2.1.4 Previous Works on Temperature-Aware Clock Distribution Design .......... 11
2.1.4.1 Dynamic Thermal Clock Skew Compensation Using Tunable Delay
Buffers [2.8] ..................................................................................................... 11
2.1.4.2 Design of Thermally Robust Clock Trees Using Dynamically Adaptive
Clock Buffers [2.9] .......................................................................................... 14
2.2 An Overview on Clock Generator...................................................................... 17
2.2.1 DLL-Based Clock Generator [2.10] ........................................................... 17
2.2.2 PLL-Based Clock Generator [2.11] ............................................................ 18
2.2.3 Multi-Phase Clock Generator Based on a Time-to-Digital Converter [2.12]
.............................................................................................................................. 19
2.2.4 Programmable Clock Generator Based on a Cyclic Clock Multiplier [2.13]
.............................................................................................................................. 20
Chapter 3 Unified Logical Effort Models over Wide Supply Voltage and
Temperature Range ................................................................................................... 22
3.1 Introduction ........................................................................................................ 22
3.2 Classic Logical Effort Model [3.3] .................................................................... 24
3.3 Unified Logical Effort Models ........................................................................... 26
3.3.1 Strong-Inversion (Super-Threshold) Region .............................................. 28
3.3.2 Moderate-Inversion (Near-Threshold) Region ........................................... 29
3.3.3 Weak-Inversion (Sub-Threshold) Region ................................................... 31
3.4 Experimental Result ........................................................................................... 33
3.4.1 Test Vehicle I ............................................................................................... 34
3.4.2 Test Vehicle II ............................................................................................. 36
Chapter 4 A Thermally Robust Buffered Clock Tree Using Logical Effort
Compensation ............................................................................................................. 39
4.1 Introduction ........................................................................................................ 40
4.2 Creating Constant Gate Delay against Thermal Variation ................................ 43
4.2.1 Effects of Dynamically Tuning MOSFET Width on Logical Effort .......... 43
4.2.2 Creating Constant Gate Delay .................................................................... 45
4.3 A Thermally Robust Buffered Clock Tree Using Logical Effort Compensation
................................................................................................................................. 48
4.4 Simulation Results ............................................................................................. 50
Chapter 5 A Programmable Clock Generator for Sub- and Near-Threshold DVFS
System ......................................................................................................................... 53
5.1 Introduction ........................................................................................................ 54
5.2 System Architecture ........................................................................................... 55
5.3 Variation-Aware Logic Design ........................................................................... 59
5.3.1 Sub-Threshold Logic Design Challenge ..................................................... 59
5.3.2 Mitigating Variation by Upsizing Transistors ............................................. 60
5.4 PVT Compensation for Locking Range of Delay Line ..................................... 61
5.4.1 Delay Ratio of FO1-INV to FO2-NAND ................................................... 62
5.4.2 Procedure of PVT Compensation for Locking Range of Delay Line ......... 64
5.5 Circuit Description ............................................................................................. 68
5.5.1 Lock-In Delay Line (LIDL) Controller ....................................................... 68
5.5.2 Lock-In Delay Line (LIDL) ........................................................................ 69
5.5.3 Pulse Generator ........................................................................................... 71
5.5.4 SEL Generator ............................................................................................. 71
5.5.5 Phase Detector ............................................................................................ 72
5.5.6 Frequency Divider ...................................................................................... 73
5.6 Combination of Clock Generator and Clock Tree ............................................. 74
5.7 Design Implementation ...................................................................................... 75
5.8 Simulation Results ............................................................................................. 76
Chapter 6 Conclusions and Future Work ................................................................ 80
6.1 Conclusions ........................................................................................................ 80
6.2 Future Work ....................................................................................................... 81
Bibliography ............................................................................................................... 83
References of chapter 1
[1.1] S. K. Gupta, A. Raychowdhury and K. Roy, “Digital computation in subthreshold region for ultralow-power operation: a device-circuit-architecture codesign perspective,” Proceeding of the IEEE, Feb. 2010, pp. 160-190.
[1.2] L. Chang, D. J. Frank, R. K. Montoye, S. J. Koester, B. L. Ji, P. W. Coteus, R. H. Dennard and W. Haensch, “Practical strategies for power-efficient computing technologies,” Proceeding of the IEEE, Feb. 2010, pp. 215-236.
[1.3] B. H. Calhoun, J. F. Ryan, S. khanna, M. Putic, J. Lach, “Flexible circuits and architectures for ultralow power,” Proceeding of the IEEE, Feb. 2010, pp. 267-282.
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[1.5] D. Markovic, C. C. Wang, L. P. Alarcon, T.-T. Liu, J. M. Rabaey, “Ultralow-power design in near-threshold region,” Proceeding of the IEEE, Feb. 2010, pp. 237-252.
References of chapter 2
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[2.9] T. Ragheb, A. Ricketts, M. Mondal, S. Kirolos, G. M. Links, V. Narayanan, and Y. Massoud, “Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers,” IEEE Transactions on Circuits and System I, vol. 56, Feb. 2009, pp. 374–383.
[2.10] J. Koo, S. Ok, and C. Kim, “A low-power programmable DLL-based clock generator with wide-range antiharmonic lock,” IEEE Trans. on Circuits and Systems II, vol. 56, no. 1, Jan. 2009, pp. 21-25.
[2.11] C.-Y. Yang, C.-H. Chang and W.-G. Wong, “A △ - Σ PLL-based spread-spectrum clock generator with a ditherless fractional topology,” IEEE Trans. on Circuits and Systems I, vol. 56, no. 1, Jan. 2009, pp. 51-59.
[2.12] D. Shin, J. Koo, W.-J. Yun, Y. J. Choi and C. Kim, “A fast-lock synchronous multi-phase clock generator based on a time-to-digital converter,” IEEE International Symposium on Circuits and Systems, May 2009, pp 1-4.
[2.13] W.-M. Lin, C.-C. Chen and S.-I. Liu, “An All-Digital Clock Generator for Dynamic Frequency Scaling,” in Int. Symp. VLSI Design, Automation and Test, July 2009, pp. 251-254.
References of chapter 3
[3.1] B. H. Calhoun, S. Khanna, R. Mann, and J. Wang, “Sub-threshold circuit design with shrinking CMOS devices,” IEEE Int’l Symp. Circuits and Systems, May 2009, pp. 2541-2544.
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[3.3] Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. San Francisco, CA: Morgan Kaufmann, 1999.
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[3.7] C.-H. Wu, S.-H. Lin, H. Chiueh, “Logical Effort Model Extension with Temperature and Voltage Variations,” 14th Int’l Workshop on THERMINIC, Sep. 2008, pp. 85-88.
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References of chapter 4
[4.1] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variation and impact on circuits and microarchitecture,” in Proc. Design Autom. Conf., 2003, pp. 338–342.
[4.2] T. Ragheb, A. Ricketts, M. Mondal, S. Kirolos, G. M. Links, V. Narayanan, and Y. Massoud, “Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers,” IEEE Transactions on Circuits and System I, vol. 56, Feb. 2009, pp. 374–383.
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References of chapter 5
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[5.6] J. Koo, S. Ok, and C. Kim, “A low-power programmable DLL-based clock generator with wide-range antiharmonic lock,” IEEE Trans. on Circuits and Systems II, vol. 56, no. 1, Jan. 2009. pp. 21-25.
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