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研究生:何承曄
研究生(外文):Ho, Cheng-Yeh
論文名稱:應用於三維積體電路之矽穿孔延遲測量器
論文名稱(外文):A TSV Delay Meter for 3D ICs
指導教授:江蕙如江蕙如引用關係蔡嘉明
指導教授(外文):Jiang, Hui-RuTsai, Chia-Ming
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:42
中文關鍵詞:三維積體電路矽穿孔技術
外文關鍵詞:3D ICThrough-silicon viaTSV
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近年來,隨著半導體製程的不斷進步,電晶體大小已微縮至奈米規模。另一方面,隨著微影製程的困難度愈來愈高,造成新一代製程的製造成本急遽上升。在成本和效能為考量目的之下,工程師們試著將晶片堆疊起來,並建構SiP的概念使晶片效能提升、面積縮小。這些堆疊的晶片便是所謂的三維積體電路。其中,負責層與層之間訊號與電源連線的矽穿孔技術扮演著極為重要的角色,利用矽穿孔技術可以大幅縮短線長,提升晶片效能。
受到製程變異影響,訊號通過兩根相同TSV時會產生延遲時間差,可能造成同步電路系統準確度受到影響。在此篇論文中,我們設計了一個矽穿孔延遲測量器電路,它可以準確地計算訊號間的延遲時間差,協助後段電路調整此延遲時間差以降低訊號間的延遲誤差。
我們運用台積電90nm CMOS製程進行HSpice模擬,此電路的最大精確度約0.74ps,模擬結果顯示延遲誤差小於0.74ps,證明電路確實能精準算出延遲時間差;此外,此電路的電晶體使用個數約1200個,和一個數位電路系統動輒數百萬顆電晶體相比,成本非常小,適合嵌於三維積體電路中作為測試電路。
The manufacturing cost of the advanced process technology rises rapidly; on the other hand, the design complexity of modern designs also increases. To conquer the high cost of a large scale design, the stacked 3D IC is developed. Through-silicon-vias (TSVs) are widely used for vertical interconnection between layers in 3D ICs. Due to process variation, even when a signal passes through two different paths composed of the same series of TSVs, these two paths may incur a delay difference and affect the accuracy of a synchronous system. In this thesis, we present a TSV Delay Meter for calculating delay difference between two paths by HSpice with TSMC 90nm CMOS process. Our results show that the maximum resolution of the meter is about 0.74ps and the simulated delay errors are lower than 0.74ps as well. Hence, the TSV Delay Meter can precisely detect delay difference.
Abstract (Chinese) i
Abstract ii
Acknowledgements iii
List of Tables vi
List of Figures vii
Chapter 1. Introduction 1
1.1 Background………………………………………………………………….1
1.2 Our Contribution…………………………………………………………….7
1.3 Organization…………………………………………………………………7
Chapter 2. TSV Model and Problem Formulation 8
2.1 TSV Technology…………………………………………………………….8
2.2 TSV Model…………………………………………………………………10
2.3 Problem Formulation……………………………………………………….13
Chapter 3. TSV Delay Meter 14
3.1 Full Structure of TSV Delay Meter……………….………………………...14
3.2 Coarse Delay Detector…………………………………………………...…15
3.3 Fine Delay Detector……………………………...…………………………20
3.4 Calculation of Delay Difference Time……………………………………...23
3.5 Simplified Structure of TSV Delay Meter………..………………………...25
Chapter 4. Simulation Results 26
4.1 Resolution Issue…………………………………………………………….26
v
4.2 Application for Heterogeneous Integration…………………………………33
4.3 Discussions………………………………………………………………….37
Chapter 5. Conclusions 39
5.1 Conclusions…………………………………...…………………………….39
5.2 Future Work…………………………………………………………………40
Bibliography 41
[1] N. Tanaka et al., “Ultra-Thin 3D-Stacked SiP Formed Using Room-Temperature Bonding between Stacked Chips,” in Proc. 55th Electronic Components and Technology Conference, pp. 788-794, 2005.
[2] Jun So Pak, Chunghyun Ryu, and Joungho Kim, “Electrical Characterization of Trough Silicon Via (TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation,” International Conference on Electronic Materials and Packaging, pp. 1-6, 2007.
[3] Sung Kyu Lim, “TSV-Aware 3D Physical Design Tool Needs for Faster Mainstream Acceptance of 3D ICs,” Design Automation Conference Knowledge Center Article, 2010.
[4] Zheng Xu, A. Beece, K. Rose, Tong Zhang, and Jian-Qiang Lu, “Modeling and Evaluation for Electrical Characteristics of Through-Strata-Vias (TSVs) in Three-Dimensional Integration,” IEEE International Conference on 3D System Integration, pp. 1-9, 2009.
[5] Philip Garrou, “3-D ICs Enter Commercialization,” Semiconductor International Mag., pp. 44-49, Nov. 2008.
[6] S.W.R. Lee, R. Hon, S.X.D. Zhang, and C.K. Wong, “3D Stacked Flip Chip Packaging with Through Silicon Vias and Copper Plating or Conductive Adhesive Filling,” in Proc. 55th Electronic Components and Technology Conference, pp. 795-801, 2005.
[7] C.H. Yun, J.R. Martin, E.B. Tarvin, and J.T. Winbigler, “Al to Al Wafer Bonding for MEMS Encapsulation and 3-D Interconnect,” IEEE 21st International Conference on Micro Electro Mechanical Systems, pp. 810-813, 2008.
[8] Uksong Kang et al., “8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology,” IEEE International Solid-State Circuits Conference - Digest of Technical Papers, pp. 130-131, 131a, 2009.
[9] L. Cadix et al., “Modeling of Through Silicon Via RF Performance and Impact on Signal Transmission in 3D Integrated Circuits,” IEEE International Conference on 3D System Integration, pp. 1-7, 2009.
[10] C. Bermond et al., “High Frequency Characterization and Modeling of High Density TSV in 3D Integrated Circuits,” IEEE Workshop on Signal Propagation on Interconnects, pp. 1-4, 2009.
[11] Dongsuk Shin, Janghoon Song, Hyunsoo Chae, and Chulwoo Kim, ”A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL with a Wide Range and High Resolution DCC,” IEEE Journal of Solid-State Circuits, pp. 2437-2451, 2009.
[12] Inhwa Jung et al., “A 0.004-mm2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor,” IEEE Transactions on Circuits and System, pp. 116-120, 2008.
[13] Chunghyun Ryu et al., “High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging,” Electronics Systemintegration Technology Conference, pp. 215-220, 2006.
[14] Dong Min Jang et al., “Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV),” in Proc. 57th Electronic Components and Technology Conference, pp. 847-852, 2007.
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