|
Reference [1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, J., 46, 1288 (1967). [2] Seiichi Aritome, “Advanced Flash Memory Technology and Trends for Files Storage Application”, pp.763, IEDM 2002. [3] D.J. Jung, “Highly Manufacturable 1T1C 4Mb FRAM with Novel Sensing Scheme”, pp.279-282, IEDM 1999. [4] “Advanced Memory Technology and Architecture”, short course, IEDM 2001. [5] S. Lai and T. Lowrey, “OUM- A 180nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications”, pp.803, IEDM 2001. [6] Paolo Cappelletti, “Flash Memories”, Kluwer Academic Publishers, 1999. [7] Pier Luigi Rolandi et al, “A 4-bit/cell Flash Memory Suitable for Stand-Alone and Embedded Mass Storage Applications”, pp.75, Non-Volatile Semiconductor Memory Workshop, Monterey, CA 2000. [8] A.J. Walker et al, “ 3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications”, 2003 Symposium on VLSI Technology. [9] Takuya Kitamura et al, “ A Low Voltage Operating Flash Memory Cell with High Coupling Ratio Using Horned Floating Gate with Fine HSG”, pp.104-105, 1998 Symposium on VLSI Technology. [10] A.Fazio, “0.13um Logic+Flash: Technology and Applications”, Non-Volatile Semiconductor Memory Workshop, Monterey, CA 2000. [11] Stephen Keeney, “A 130nm Generation High Density ETOXTM Flash Memory Technology,” IEDM Tech. Dig., p.41-44,2001. [12] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transactions on Nanotechnology., vol. 1, pp. 72-77, 2002. [13] M. H. White, D. A. Adams, J. Bu, “On the Go with SONOS,” IEEE Circuits and Devices Magazine., vol. 16, pp. 22-31, 2000. [14] H.E. Maes, J.S. Witters, G. Groeseneken, "Trends in non-volatile memory devices and technologies", Proceedings of the 17th ESSDERC-conference,Invited paper, pp. 743-754, 1987, and in Solid State Devices, North Holland Publishing Company, Eds. G. Soncini, P.U. Calzolari, pp. 157-168, 1987. [15] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage,” IEEE Int. Electron Devices Meeting Tech. Dig., pp. 521-524, 1995. [16] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, Y. Lee, “Room temperature operation of a quantum-dot flash memory,” IEEE Electron Device Letters., vol.18, pp. 278-280, 1997. [17]Y. C. King, T. J. King, C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex,” IEEE Int. Electron Devices Meeting Tech. Dig., pp.115-118, 1998. [18] S. Lai, “Tunnel Oxide and ETOX Flash Scaling Limitation,” IEEE International Non –Volatile Memory Conference, pp. 6 -7, 1998. [19] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O'Connell, R. E. Oleksiak, “The variable threshold transistor, a new electrically alterable nondestructive read-only storage device,” presented at the Internat'l Electron Devices Meeting, 1967. [20] “Test and Test equipment” in The International Technology Roadmap for Semiconductors (ITRS), 2001, pp.27-28. [21] Y.N. Tan, W.K. Chim, W.K. Choi, M.S. Joo, T.H. Ng, and B.J. Cho, “High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., 2004, pp.889-892. [22] W.J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di. “Current Transport in Metal/Hafmium Oxide/Silicon Structure,” IEEE electron Device Letters., vol.23, no.2, pp.97-99, Feb. 2002. [23] G. D. Wilk, R.M. Wallace, J.M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations”, Applied Physics Review, vol.89, no. 10, pp.5243-5275, Nay 2001. [24] T.Sugizaki, M.Kobayashi, M.Ishidao, H.Minakata, “Novel Multi-bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer”, Symposium on VLSI Technology Digest of Technical Papers, 2003. [25] M. White et al., IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 20, p.190, 1997. [26]H.-H. Tseng, P. G.Y. Tsui, P. J. Tobin, J. Mogab, M. Khare, X.W. Wang, T. P. Ma, R. Hegde, C. Hobbs, J. Veteran, M. Hartig, G. Kenig, V. Wang, R. Blumenthal, R.Cotton, V. Kaushik, T. Tamagawa, B. L. Halpern, G. J. Cui, J. J. Schmitt, “Application of JVD nitride gate dielectric to a 0.35 micron CMOS process for reduction of gate leakage current and boron penetration,” in IEDM Tech. Dig., pp. 647-650, 1997. [27]A. Melik-Martirosian, T. P. Ma, X. W. Wang, X. Guo, F. P. Widdershoven, D. R. Wolters, V. J.D. van der Wal, M. J. van Duuren, ”Demonstration of a flash memory cell with 55 A EOT silicon nitride tunnel dielectric,” in Symp. VLSI Tech. Dig., pp. 138 -141, 2001. [28]Y. Shi, X. Wang, T. P. Ma, “Electrical properties of highquality ultrathin nitride/oxide stack dielectrics, IEEE Transactions on Electron Devices, vol. 46, pp. 362-368, 1999. [29]J. Kim, J. D. Choi, W. C. Shin, D. J. Kim, H. S. Kim, K. M. Mang, S. T. Ahn, O. H. Kwon, “Scaling down of tunnel oxynitride in NAND flash memory: oxynitride selection and reliabilities, in Proc. IRPS, pp. 12-16, 1997. [30]U. Sharma, R. Moazzami, P. Tobin, Y. Okada, S. K. Cheng, J. Yeargain, “Vertically scaled, high reliability EEPROM devices with ultra-thin oxynitride films prepared by RTP in N2O/O2 ambient, in IEDM Tech. Dig., pp. 461-464, 1992. [31] P. Pavan, R. Bez, P. Olivo, E. Zanoni, “Flash memory cells—An overview,” Proc. IEEE, vol. 85, pp. 1248-1271, 1997. [32] M. Woods, “Nonvolatile Semiconductor Memories: Technologies, Design, and Application,” C. Hu, Ed. New York: IEEE Press, (1991) ch. 3, pp. 59. [33] P. E. Cottrell, R. R. Troutman, T. H. Ning, “Hot-electron emission in n-channel IGFET's,” IEEE Journal of Solid-State Circuits, vol. 14, pp. 442-455, 1979. [34] B. Eitan, D. Froham-Bentchkowsky, “Hot-Electron. Injection into the Oxyde in N-Channel MOS devices,” IEEE Transaction on Electron Devices., vol. 28, pp. 328-340, 1981. [35] J. Bu, M. H. White, “Design considerations in scaled. SONOS nonvolatile memory devices,” Solid State Electronics., vol. 45, pp. 113-120, 2001. [36] M. L. French, M. H. White, “Scaling of multidielectric nonvolatile SONOS memory structures,” Solid-State Electron., vol. 37, pp. 1913-1923, 1994. [37] M. L. French, C. Y. Chen, H. Sathianathan, M. H. White, “Design and scaling of a SONOS Multidielectric device for nonvolatile memory applications,” IEEE Trans. Comp. Pack. And Manu. Tech., part A, vol. 17, no. 3, pp. 390-397, 1994. [38] Y. Wang, M. H. White, “An analytical retention model for SONOS nonvolatile memory devices in the excess electron state,” Solid-State Electron., vol.49, pp.97-107, 2005. [39] Y. S. Hisamune, K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani, T. Okazawa, “A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mb and future flash memories,” in IEDM Tech. Dig., 1993, pp. 19-22. [40] Z. Liu, C. Lee, V. Narayanan, G. Pei, E. C. Kan, “Metal nanocrystal memories—part I: device design and fabrication,” IEEE Transaction on Electron Devices, vol. 49, no. 9, pp. 1606-1613, 2002. [41] J. L. Moll, Physics of Semiconductors, McGraw-Hill, New York, 1964. [42] S. M. Sze, Physics of Semiconductor Devices, p. 497-498, Wiley, New York , 1981. 81[43] C. Svensson, I. Lundstrom, “Trap-assisted charge injection in MNOS structures,”Journal of Applied Physics., vol. 44, pp. 4657-4663, 1973. [44] Chan C. and Lien J. (1897) “Corner-field induced drain leakage in thin oxide MOSFETs”. IEDM Technical Digest, p.714. [45] Chan T.Y., Chen J., Ko P.K. and Hu C. (1987) “The impact of gate-induced leakage current on MOSFET scaling”, IEDM Technical Digest, p.718. [46] I. C. Chen, C. Kaya, J. Paterson, “Band-to-Band Tunneling Induced Substrate Hot Electron (BBISHE) Injection: A New Programming Mechanism for Non-Volatile Memory. Devices,” in IEDM Technical Digest, pp. 263-270, 1989. [47] Yakov Roizin, Micha Gutman, Efraim Aloni, Victor Kairys, Pavel Zisman,“Retention Characteristic of micro FLASH Memory (Activation Energy of Traps in the ONO stack)” [48] K. Kim, J. Choi, NVSMW, pp.9, 2006 [49] Y. Wang, M. H. White, “An analytical retention model for SONOS nonvolatile memory devices in the excess electron state,” Solid-State Electron., vol.49, pp.97-107, 2005. [50] R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, “Introduction to Flash Memory,” In Proc. Of the IEEE, vol. 91, no. 4, pp. 489-502, 2003. [51] P. Cappelletti, R. Bez, D. Cantarelli, L. Fratin, “Failure mechanisms of Flash cell in program/erase cycling,” in IEDM Tech. Dig., 1994, pp. 291-294. [52] T. Yamaguchi et al., IEDM Technical Digest, p.19, 2000. [53] W. Zhu et al., IEDM Technical Digest, p.463, 2001. [54] M. H. White, L. Yang, A. Purwar, and M. L. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Trans. Comp. Packag. Manufact. Technol. A, vol. 20, pp. 190–195, Mar. 1997. [55] G. D.Wilk, R. M.Wallace, and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations,” J. Appl. Phys., vol. 89, pp.5243–5275, 2001. [56] H. Wann, C. Hu, IEEE Electron Device Lett. 16 (1995 May) 491. [57] M.H. White, D.A. Adams, B. Jiankang, IEEE Circuits DeviceS Mag.16(2000 Jan) 22. [58] U. Sharma, R. Moazzami, P. Tobin, Y. Okada, S. K. Cheng and J. Yeargain, “Vertically Scaled, High Reliability EEPROM Devices with Ultra-thin Oxynitride Films Prepared by RTP in N20/02 Ambient,” IEEE IEDM, Tech. Dig., 1992, pp. 461-464. [59] H. Fukuda, M. Yasuda, T. Iwabuchi and S. Ohno, “Novel N2O-Oxynitridation Technology for Forming Highly Reliable EEPROM Tunnel Oxide Films,” IEEE Electron Device Lett., Vol. 12, 1991, pp. 587-589. [60] B. C. Lin, K. M. Chang, C. H. Lai, K.Y. Hsieh and J. M. Yao, “Reoxidation Behavior of High-Nitrogen Oxynitride Films after O2 and N2O Treatment,” Jpn. J. Appl. Phys., vol. 44, pp.2993-2994, 2005. [61]J. Kim, S. T. Ahn, “Improvement of the tunnel oxide quality by a low thermal budget dual oxidation for flash memories,” IEEE Electron Device Letters, vol.18, no. 8, pp. 385-387, Aug. 1997. [62] J.L. Wu, H.C. Chien, C.W. Liao, C.H. Kao, “Comparison of Electrical and Reliability Characteristics of Different Tunnel Oxides in SONOS Flash Memory,” IEEE International Workshop on Memory Technology, Design, and Testing (MTDT’06),2006. [63] Y.N. Tan, W.K. Chim, B.J. Cho, W.K. Choi, “Over-Erase phenomenon in SONOS-Type flash memory and its minimization using a Hafnium oxide charge storage layer,” IEEE Transactions on Electron Devices, vol.51, No.7, July 2004. [64] Y.H. Lin, C.H. Chien, C.Y. Chang, T.F. Lei, “Annealing temperature effect on the performance of nonvolatile HfO2 Si-oxide-nitride-oxide-silicon-type flash memory,” J. Vac. Sci. Technol. A, Vol.24, No. 3, May/Jun 2006. [65] H.A.R. Wegener, A.J. Lincoln, H.C. Pao, M.R. O’Connell, and R.E. Oleksiak, The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEEE IEDM Tech. Dig., Washington, D.C., 1967. [66] T.Y.Chan, K.K.Young and C.Hu, “A true single-transistor oxide- nitride-oxide EEPROM device”. IEEE Electron Device Letters, vol.8, no.3, pp.93-95, 1987. [67] M.K. Cho and D.M.Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology”, IEEE Electron Device Letters, pp.399-401, Vol.21, No.8, 2000. [68] I. Fijiwara, H.Aozasa, K.Nomoto, S.Tanaka and T.Kobayashi, “ High speed program/erase sub 100nm MONOS memory cell”, Proc. 18th Non-Volatile Semiconductor Memory Workshop, p. 75, 2001. [69] H. Reisinger, M. Franosch, B. Hasler, and T. Bohm, Symp. on VLSI Tech. Dig. , 9A-2, 113 (1997). [70] C. Tung-Sheng, W. Kuo-Hong, C. Hsien, and K. Chi-Hsing, “Performance improvement of SONOS memory by bandgap engineering of charge-trappinglayer”, IEEE Electron Device Lett., vol. 25, no. 3, pp.205–207, Mar. 2004. [71] Y. N. Tan, W. K. Chim, and B. J. Cho, W. K. Choi, “Over-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer”, IEEE Transations on Eelectron Devices, vol.51, no.7, July 2004. [72] Min She, Hideki Takeuchi, and Tsu-Jae King, “Silicon-Nitride as a Tunnel Dielectric for Improved SONOS-Type Flash Memory”, IEEE Electron Device Letters, vol. 24, no. 5, MAY 2003. [73] Chang-Hyun Lee, Kyu-Charn Park, and Kinam Kim, “Charge-trapping memory cell of SiO2/SiN/high-k dielectric Al2O3 with TaN metal gate for suppressing backward tunneling effect”, Applied Physics Letters 87, 073510 (2005) [74] Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, and Ping-Hung Yeh, “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels”, Applied Physics Letters 90, 122111 (2007) [75] Peiqi Xuan, Min She, Bruce Harteneck, Alex Liddle, Jefkey Bokor, and Tsu-Jae King, “FinFET SONOS Flash Memory for Embedded Applications”, IEEE IEDM 609-612 (2003). [76] Tzu-Hsuan Hsu, Hang Ting Lue, Ya-Chin King, Jung-Yu Hsieh, Erh-Kun Lai, Kuang-Yeu Hsieh, and Chih-Yuan Lu, “A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for NAND-Type Flash Memory”, IEEE Electron Device Letters, vol. 28, no. 5, MAY 2007. [77] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and Doug Buchanan, IEDM Tech. Dig., p.521 (1995) [78] Yan Ny Tan, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 4, APRIL 2006 [79] Chao Sung Lai, APPLIED PHYSICS LETTERS 86, 222905 2005 [80] Chih-Ren Hsieh, APPLIED PHYSICS LETTERS 96, 022905 2010
|