在本論文中，主要探討薄膜型SANOS結構快閃記憶體在三維積體電路設計(3D-ICs)製程中的可行性。在三維積體電路製程，低溫製程是需要被討論並導入，所以我們將傳統SONOS結構快閃記憶體改成薄膜型，並期許將記憶體元件尺寸微縮至五十奈米，以增加在積體電路製程上單一面積的元件陣列密度，提升可記憶位元。
在第一部分，五十奈米線寬薄膜型SANOS快閃記憶體,我們導入氧化鋁(Al2O3)代替TEOS，這目的是為了改善元件閘極射入漏電流現象(Gate injection)與持久性(Retention)。同時在量測元件上發現，因為元件尺寸小，在元件通道內可能沒有晶界(grain boundary)，加上魚鰭型元件(Finfet)可增強對通道之電場的特性，以上原因使得小線寬薄膜型SANOS結構快閃記憶體在電性上接近傳統矽基板(Bulk silicon)元件水準，在記憶能力方面，甚至比矽基板記憶體還好，大的記憶視窗、較好的耐用度(Endurance)與持久性。對小線寬薄膜型SANOS結構快閃記憶體在150度下量測，記憶視窗在十年線的標準也還有2.4伏特。
第二部分探討微波氧化作用(Microwave Oxidation)，我們導入微波氧化作用為的是得到低溫氧化層，期許這低溫氧化層可導入薄膜型SONOS結構快閃記憶體中取代原本的熱製程穿隧氧化層(Thermal Tunneling layer)。在微波氧化製程中配合上susceptor與碳化矽板，得到在腔體內均勻微波與保持足夠的製程溫度，實驗的最後我們可以得到3.5奈米的氧化層。比較高溫爐管氧化層，對氧化層品質方面也不會差高溫爐管氧化層太多。然而在氧化層均勻度上確實有改善空間，製程的邊緣效應讓晶圓邊緣處氧化層稍薄，這是未來需要持續研究的部分。

In this thesis, we discuss the feasibility of TFT SANOS memory devices in three dimension-integrated circuits (3D-ICs). For 3D-ICs, low temperature fabrication process is necessary. Therefore, one stacked conventional SONOS devices on poly-Si films, them the designation of thin film transistor (TFT) SONOS devices. The dimensions of TFT SANOS devices were scaled down to sub-50 nm in order to increase the chip density and memory bits.
In first part, for the fabrication of sub-50nm TFT SANOS devices, we used Al2O3 to replace TEOS for the blocking layer of SONOS structure, as named SANOS structure. This layer could prevent gate injection (gate leakage current) and improve device retention ability. For electrical measurement, there are two advantages of TFT SANOS devices that could be addressed. One is that the tri-gate structure enhances the electrical field during programming and erasing periods. The other one is that there are no grain boundaries inside the channel of nanometer TFT SANOS devices. Due to the advantages, the quasi-FinFET SANOS devices get similar electrical characteristics as bulk-Si SONOS devices. These devices also have good reliability characteristics, with a memory window of 2.6V in ten years at 150OC.
The second part was about microwave oxidation, we used a microwave system to grow a pure SiO2 layer at low temperature. One would like to use microwave oxide as the thermal tunneling oxide of TFT SANOS devices. In this study, we used microwave susceptors and silicon carbide wafers to enhance microwave oxidation, which causes more suitable temperature process with better microwave distribution. During a series experiments, one get a about 3.6 nm thick oxide layer. As compared with that by furnace, the oxide quality by microwave anneal was about the same as that by thermal process. But, the uniformity of microwave oxidation still needs to be improved.

Chinese Abstract i
English Abstract iii
Acknowledgement v
Contents vi
Table Captions viii
Figure Captions ix
Chapter 1 Introduction 1
1.1 Evolution of Flash Memory 1
1.1-1 Floating Gate non-Volatile Memory 1
1.1-2 SONOS non-volatile memory 2
1.2 Three Dimension-Integrated Circuits (3D-ICs) 2
1.3 Motivations 4
1.4 Organization 5
Chapter 2 Device Fabrication and Operation of SONOS Memory Devices 8
2.1 Thin Film Transistor SONOS-type Flash Memory 8
2.1-1 NAND 8
2.1-2 Program/Erase Mechanisms – FN Tunneling 9
2.1-2 process flow 10
2.2 Microwave Anneal and Oxidation in SONOS-type Structure 11
2.2-1 Mechanisms of Microwave Oxidation 12
2.2-2 Experiment of Oxidation 12
2.2-3 Capacitor of Process Flow 13
Chapter 3 SONOS-type TFT Flash Memory 21
3.1 Device Measurement and Operation 21
3.1-1 Basic Program/Erase Operation 21
3.1-2 Retention 21
3.1-3 Endurance 22
3.2 SEM and TEM of TFT SANOS Memory 23
3.3 Basic Characteristics of SONOS-type TFT Memory 23
3.4 Program/Erase Characteristics of TFT SANOS Memory 25
3.5 Reliability Characteristics of TFT SANOS Memory 25
Chapter 4 Microwave Low Temperature 44
4.1 Experiment Detail 44
4.2 I-V curve Characteristics of Microwave Oxidation 45
Chapter 5 Conclusion 56
5.1 Conclusion 56
5.2 Future Work 57
Reference 59

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