次/近臨界隨機存取記憶體是能源考量的單晶片系統設計中，降低功率消耗的重要方法。然而，在次/近臨界電壓區，最需要被關注的是隨機存取記憶體的穩定性和可靠性，而不是高速性。在本論文中，首先提出一個新型的8電晶體次/近臨界隨機存取記憶體，比起傳統雙埠隨機存取記憶體，它提升18%寫入跳脫點及減少68.8%寫入變異(標準差)。接著提出了一個9電晶體次臨界隨機存取記憶體能有效地被建構成位元交錯結構。為了驗證所提出架構，一個1kb位元交錯的靜態隨機存取記憶體採用聯電 65奈米技術，其一次讀/寫操作在最低能量消耗點0.3伏特時之功耗為5.824微微焦耳。第三提出了一個應用於醫療保健，極低功耗操作於0.5伏特的32kb 8電晶體隨機存取記憶體為基礎的先進先出記憶體，它採用自適應功率控制和電源閘系統，聯電90奈米技術，功耗4.81微瓦。最後，動態電源調整可根據性能要求來調節系統電壓源來降低能源消耗。一個1kb的動態電源調整8電晶體隨機存取記憶體為基礎的先進先出記憶體以聯電65奈米技術實現 0.5伏特(近臨界)和0.3伏特(次臨界)之間的運作，分別在625仟赫讀取頻率和20仟赫的寫入頻率耗功0.535微瓦和0.163微瓦。此提出的動態電源調整先進先出記憶體若一直處於低功耗模式可省下達69.5%的功率，若在低功耗模式的期間長於48.66微秒則不會有多餘的功率消耗。

Sub/Near-threshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. Nevertheless, in sub/near- threshold region, the primary concerns of SRAM are stability and reliability instead of high-speed. In this thesis, a novel 8T sub/near-threshold SRAM is presented firstly, which has 18% improvement in write margin and 68.8% reduction in write variation (standard deviation) compared to conventional dual-port SRAM. Secondly, a 9T subthreshold SRAM is proposed to efficiently enable implementation of bit-interleaving structure. A 1kb bit- interleaved SRAM is implemented in UMC 65nm technology to verify the proposed scheme, which operates at the minimum energy point of 0.3V with 5.824pJ energy consumption per read/write operation. Thirdly, an extremely low power 0.5V 32kb 8T SRAM-based FIFO memory, which employs adaptive power control system and power gating, is implemented for healthcare applications in UMC 90nm technology, with 4.81μW power consumption. Finally, dynamic voltage scaling (DVS) reduces energy consumption by adjusting system supply voltage depending on performance requirement. A 1kb DVS 8T SRAM-based FIFO memory is implemented to operate between 0.5V (near-threshold) and 0.3V (subthreshold) in UMC 65nm technology, with 0.535μW and 0.163μW power consumption, respectively, at 625kHz reading frequency and 20kHz writing frequency. The proposed DVS FIFO memory can provide up to 69.5% power savings when low-power mode is always engaged, and there is no power overhead if the period of low-power mode is longer than 48.66μs.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Challenges 2
1.3 Motivation 3
1.4 Thesis Organization 4
Chapter 2 Previous Low-Power SRAM Designs 5
2.1 Introduction 5
2.1.1 SRAM Column Circuitry 6
2.1.2 Ultra-Low Voltage SRAM 7
2.2 Power Dissipation 8
2.2.1 Dynamic Power 8
2.2.2 Leakage Power 10
2.2.3 Short-Circuit Power 14
2.3 SRAM Bit-Cell Stability 15
2.3.1 Static Noise Margin (SNM) 15
2.3.2 Write Margin (WM) 16
2.4 Conventional Symmetric 6T SRAM 17
2.4.1 Symmetric 6T SRAM Bit-Cell 17
2.4.2 Read/Write Operation 18
2.4.3 Read Disturbance 19
2.4.4 Straight Line Layout 21
2.4.5 Variation in Low Voltage 21
2.5 Well-Known Low Power Single-Port SRAM 22
2.5.1 Schmitt Trigger based subthreshold SRAM (ST-1) 23
2.5.2 Schmitt Trigger based subthreshold SRAM (ST-2) 24
2.5.3 10T Subthreshold SRAM with Bit-Interleaving Scheme 25
2.5.4 10T Subthreshold SRAM with auto-compensation (AC) 26
2.6 Well-Known Low Power Dual-Port SRAM 27
2.6.1 8T SRAM 27
2.6.2 8T Subthreshold SRAM 30
2.6.3 10T Subthreshold SRAM (I) 32
2.6.4 10T Subthreshold SRAM (II) 33
2.6.5 Sensing Amplifier Schemes 34
2.7 Summary 35
Chapter 3 A Novel 8T Sub/Near-threshold SRAM Cell Design 37
3.1 Introduction 37
3.1.1 Conventional Dual-Port SRAM Bit-Cell 37
3.1.2 Conventional Dual-Port SRAM limitation 38
3.2 A Novel 8T Sub/Near-threshold SRAM Bit-Cell 39
3.2.1 Layout Consideration 40
3.3 Read-Ability and Read-Stability Improvement 41
3.3.1 Hold SNM and Read SNM 41
3.3.2 Read-Ability Improvement 43
3.4 Write-Ability Improvement 47
3.4.1 Write Mode 47
3.4.2 Write-Ability and Write-Stability Improvement 48
3.5 Power Consumption 50
3.6 Summary 52
Chapter 4 A 1kb 9T Subthreshold SRAM with Bit-Interleaving
Scheme in 65nm CMOS 53
4.1 Introduction 53
4.2 A Novel 9T Subthreshold SRAM bit-cell 55
4.2.1 Basic Operation 56
4.2.2 Energy per Operation 57
4.2.3 Hold Mode 58
4.2.4 Read Mode 59
4.2.5 Write Mode 61
4.2.6 Layout Consideration 64
4.3 Bit-Interleaving Scheme 65
4.3.1 Soft Error 66
4.3.2 Half-Selected Disturbance 67
4.3.2 Bit-Interleaving Scheme 68
4.3.3 9T SRAM with Bit-Interleaving Scheme 69
4.4 Architecture of proposed SRAM 71
4.4.1 Address Decoders and Word-Line Driver 72
4.4.2 Read/Write Circuits 73
4.4.3 Pulse Control Circuits and Replica Column 74
4.5 Post-Layout Simulation Result 76
4.6 Summary 78
Chapter 5 A 32kb Near-threshold SRAM Based FIFO in 90nm
CMOS and a 1kb DVS FIFO in 65nm CMOS for WBANs 79
5.1 Introduction 79
5.1.1 Wireless Sensor Node for WBANs 80
5.2 Ultra-Low Power FIFO Memory 82
5.2.1 8T SRAM Storage Element 83
5.2.2 Shift Register Based Read/Write Pointer 84
5.2.3 Adaptive Power Control 87
5.2.4 Write Pulse Control Circuitry with Replica Column 89
5.2.5 Read Pulse Control Circuitry with Replica Column 91
5.3 A 32kb 0.5V SRAM-Based FIFO in 90nm CMOS 92
5.3.1 Post-Layout Simulation Result 93
5.4 A 1kb DVS SRAM-Based FIFO in 65nm CMOS 95
5.4.1 Introduction 95
5.4.1 Switched Capacitor DC-DC Converter 97
5.4.2 Supply Switch and DVS Controller 98
5.4.3 Post-Layout Simulation Result 100
5.4.4 Analysis of DVS FIFO Energy Consumption 102
5.5 Summary 104
Chapter 6 Conclusions 105
6.1 Conclusions 105
6.2 Future Work 106
Bibliography 107
7.1 Chapter 1 107
7.2 Chapter 2 107
7.3 Chapter 3 111
7.4 Chapter 4 112
7.5 Chapter 5 113
Vita 116

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