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研究生:劉聿民
研究生(外文):Liu, Yu-Min
論文名稱:具高介電常數閘極絕緣層之低溫複晶矽薄膜電晶體之研究
論文名稱(外文):Investigation on LTPS-TFTs With High-κ Gate Dielectrics
指導教授:趙天生
指導教授(外文):Chao, Tien-Sheng
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子物理系所
學門:自然科學學門
學類:物理學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:99
中文關鍵詞:薄膜電晶體高介電常數閘極絕緣層二氧化鉿轉導電導
外文關鍵詞:TFTHigh-kGate DielectricHfO2transconducatance
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在本論文中,我們製作並且研究具有不同厚度二氧化鉿閘極絕緣層的P形通道低溫複晶薄膜電晶體。我們比較了具有不同厚度二氧化鉿閘極絕緣層的P形通道低溫複晶薄膜電晶體的電性和可靠度。在電性方面,我們發現轉導電導的峰值會隨著二氧化鉿絕緣層的厚度增加而升高。這個現象違反了我們之前的認知:閘極的控制能力應會隨著閘極電容值的上升而增強。因此,造成這個現象的原因值得我們探討。我們發現具有小厚度二氧化鉿的薄膜電晶體其轉導電導的峰值會因為二氧化鉿產生相變而發生劣化;另外,具有較厚二氧化鉿閘極絕緣層的薄膜電晶體會因其中具有較多本質的帶正電荷的氧缺陷使其轉導電導的峰值獲得較大幅度地提升。最後,我們系統性地探討了閘極負偏壓高溫應力(NBTI)對具有不同厚度二氧化鉿閘極絕緣層P形通道薄膜電晶體的劣化機制,我們發現臨界電壓漂移、次臨界擺幅和轉導電導峰值的劣化主要和二氧化鉿絕緣層的厚度、應力溫度和應力偏壓的大小有關。
In this thesis, p-channel LTPS-TFTs with different thickness of the HfO2 gate dielectrics were fabricated and investigated. We compared the electrical characteristics and the NBTI reliability issue of the p-channel LTPS-TFTs with the different thickness of HfO2 gate dielectrics. As for the electrical characteristics, we found that the peak transconductance (Gm_max) increases with the HfO2-thickness. This phenomenon violates the well known knowledge that the gate control ability should be enhanced with a higher gate capacitance. Therefore, it is worthwhile to investigate the mechanism of this phenomenon. We found that the phase change of the HfO2 layers contributes to the Gm_max degradation of the TFTs with the thin HfO2 layer. Besides, it was found that the enhanced Gm_max ¬of the p-channel TFTs with the thicker HfO2 layer is related to the intrinsic charged oxygen vacancies in the HfO2 layer. Finally, the degradation mechanism of the NBTI stress was systematically studied. It was found that the behavior of Vth variation, S.S. degradation and the Gm_max degradation are mainly dependent on the thickness of the HfO2 layer, stress temperature and the stress bias.


Contents
Abstract (Chinese)……………………………………………………i
Abstract (English)………………………………........….…..ii
Acknowledgement…………………………………………………..…iii
Contents…………………………………………….……………….…iv
Table Caption………………………………………….…….…....vii
Figure Caption……………………………………………….…..vii

Chapter 1 Introduction
1.1 Overview of Thin-Film Transistors……………………………………….1
1.2 Poly-Si TFTs using High-k Gate Dielectrics……………………………...3
1.3 Negative Bias Temperature Instability of LTPS TFTs…………………...4
1.4 NBTI Stress in High-κ Gate Dielectrics…………………………………...7
1.5 Mobility Issues in High-k Dielectrics……………………………………...8
1.6 Motivation………………………………………………………………9
Chapter 1 Reference…………………………………………………………....12

Chapter 2 Experimental Details and Method of Parameter Extraction
2.1 Device Fabrication………………………………………………………...21
2.2 Measurement…………………………………………………… 22
2.3 Method of Parameter Extraction (Determination of Threshold Voltage)..22
2.3.1 Determination of subthreshold swing………………………………….....24
2.3.2 Determination of on/off current ratio…………………………………….24
2.3.3 Determination of field effect mobility……………………………………25
2.3.4 Determination of the trap state density…………………………………...26
Chapter 2 Reference…………………………………………………………..31

Chapter 3 Electrical Characteristics of the p-channel LTPs TFTs with Different Thickness of High-κ Gate Dielectrics
3.1 Electrical Characteristics............................................................................32
3.2 Material Analysis………………………………………………………….34
3.2.1 Crystallization……………………………………………………….35
3.2.2 Source/Drain sheet resistance………………………………………….....36
3.3 Oxygen Vacancy Induced Voltage Drop across the HfO2 Layer……….37
Chapter 3 Reference…………………………………………………………..51

Chapter 4 Negative Bias Temperature Instability in p-Channel LTPS TFTs with Different Thickness of HfO2 Gate Dielectrics
4.1 Gate Leakage Current……………………………………………………53
4.2 NBTI Stress………………………………………………………………..56
4.2.1 VG_stress-Vt = -3V at 25℃…………………………………………………58
4.2.2 VG_stress-Vt=-5V at 25℃…………………………………………………..62
4.2.3 VG_stress-Vt=-3V at 125℃…………………………………………………66
4.2.4 VG_stress-Vt=-4V at 125℃…………………………………………………69
Chapter 4 Reference…………………………………………………………..93

Chapter 5 Conclusion
5.1 Conclusion…………………………………………………………………96

Vita (Chinese)……………………………………………………………...…..99


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chapter 2
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chapter 3
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chapter 4
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[10] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “ Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys, vol. 53, pp.1193-1202, 1982.
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[14] C. Hu, M. Wang, B. Zhang, M. Wong,“ Negative bias temperature instability dominated degradation of metal-induced laterally crystallized p-Type polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 56, pp. 587-594, 2009.



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