臺灣博碩士論文加值系統

隨著無線通訊的蓬勃發展，應用於無線通訊中的類比數位轉換器也受到更多的矚目。相對於其他類比數位轉換器而言，三角積分 (Delta-sigma) 類比數位轉換器擁有較佳的頻寬和解析度。
其中連續時間三角積分類比數位轉換器比起離散時間三角積分類比數位轉換器更為受重視，因為其有著更低的功率消耗及較大的訊號頻寬，更適合被廣泛應用於無線通訊中。
在此篇論文中，連續時間調變器的設計流程將被呈現。首先，我們實現一應用於藍芽技術之設計。其具有1 MHz 訊號頻寬及最大訊號雜訊失真比(SNDR)為58.3 dB 的電路。此電路使用電阻取代原先轉導當作零點轉移的功用，以節省面積和功率。而另一個設計使用了前饋控制架構，此電路具有3 MHz的訊號頻寬及最大訊號雜訊失真比56.3 dB。
晶片以台積電180 奈米互補式金氧半導體製程所製造。模擬結果顯示第一顆晶片操作在100 MHz 取樣頻率下，消耗9.1 mW 的功率在1.8 V的供應電壓下。模擬結果顯示另一顆晶片操作在100 MHz 取樣頻率下，消耗11.8 mW 的功率在1.8 V的供應電壓下。

With the growth of wireless communication, there has been more focus on the analog-to-digital converter (ADC) for wireless applications. Compare with the other
analog-to-digital converters, Delta-sigma converters have better signal bandwidth and resolution. The continuous-time delta-sigma ADCs get growing interests in wireless applications because of its lower power consumption and wider bandwidth as compared with the discrete-time counterparts.
In this thesis, the design of the continuous-time modulator is presented. First of all, we fulfill a design for Bluetooth application. It achieves 58.3 dB SNDR within a
1 MHz signal bandwidth. This work replaces the transconductor with resistors as the
function of zero shifts to save chip area and power consumption. Another design takes the feedforward architecture and it only achieves 56.3 dB SNDR within a
3 MHz signal bandwidth.
Both chips have been fabricated by TSMC 180 nm CMOS process. The simulated results show that the first work consumes 9.1 mW with 100 MHz sample rate in 1.8 V supply voltage. The second work consumes 11.8 mW with 100 MHz
sample rate in 1.8 V supply voltage.

CHAPTER 1 Introduction................................1
1.1 Motivation..................................1
1.2 Thesis Overview.............................2

CHAPTER 2 Overview of Oversampling ΔΣ Modulator......4
2.1 Performance Parameters......................4
2.1.1 Signal-to-Noise Ratio (SNR).................4
2.1.2 Signal-to-Noise and Distortion Ratio (SNDR).4
2.1.3 Spurious Free Dynamic Range (SFDR)..........5
2.1.4 Dynamic Range (DR)..........................5
2.1.5 Effective Number of Bits (ENOB).............6
2.2 Sampling Theorem and Quantization...........6
2.3 Oversampling...............................11
2.4 Noise Shaping..............................12
2.4.1 First-Order Delta-Sigma Modulator..........13
2.4.2 Second-Order Delta-Sigma Modulator.........15
2.4.3 Higher-Order Delta-Sigma Modulator.........17
2.4.4 Multi-Stage (Cascade, MASH) Modulator......18

CHAPTER 3 Design of Continuous-Time ΔΣ Modulator....20
3.1 Discrete-Time and Continuous-TimeΔΣ
Modulators.................................20
3.2 Transformation of a DT DSM to a CT DSM ....22
3.3 Non-idealities in Delta-Sigma Modulator....25
3.3.1 Non-idealities of CT Integrators...........25
3.3.2 Variation of RC Time Constant..............27
3.3.3 Excess Loop Delay..........................27
3.3.4 Clock Jitter...............................30
3.3.5 Multi-bit DAC Element Mismatch.............32

CHAPTER 4 A Continuous-Time Transconductor-Capacitor
Delta-Sigma Modulator Using
feedback Resistors.........................34
4.1 System Level Design........................34
4.1.1 Loop Filter Architecture...................34
4.1.2 Non-idealities Simulation..................38
4.1.3 System Level Simulation....................40
4.2 Circuit Level Design.......................40
4.2.1 Loop Filter................................40
4.2.2 The First Stage-Active-RC Integrator.......41
4.2.3 The Remain Stages-Gm-C Integrator..........43
4.2.4 Resonator-Feedback Resistor................46
4.2.5 Comparator.................................47
4.2.6 Current Steering DAC.......................48
4.2.7 Tuning Circuit.............................49
4.2.8 Low Jitter Clock Generator.................50
4.3 Circuit Level Simulation...................51
4.4 Layout Design..............................52

CHAPTER 5 A Feedforward Fourth-Order Continuous Time
Delta-Sigma ADC with 3 MHz Bandwidth.......55
5.1 Feedforward (FF) and Feedback (FB)
Topologies.................................55
5.2 Mason’s Gain Rule.........................56
5.3 System Level Design........................59
5.3.1 Loop Filter Architecture...................59
5.3.2 Non-idealities Simulation..................60
5.3.3 System Level Simulation....................64
5.4 Circuit Level Design.......................64
5.4.1 Loop Filter................................64
5.4.2 Integrator.................................65
5.4.3 Summation Circuit..........................67
5.4.4 Comparator and Flash ADC...................70
5.4.5 Current Steering DAC.......................71
5.5 Circuit Level Simulation...................75
5.6 Layout Design..............................76

CHAPTER 6 Test Setup and Experimental Results........79
6.1 Measuring Environment......................79
6.1.1 Power Supply Regulator.....................81
6.1.2 Single-to-Differential Transformer.........82
6.2 PCB and Pin Configurations.................82
6.3 Measurement................................85
6.3.1 A Continuous-Time Transconductor-Capacitor
Delta-Sigma Modulator Using
Feedback Resistors.........................85
6.3.2 A Feedforward Fourth-Order Continuous-Time
Delta-Sigma ADC with 3 MHz Bandwidth.......87
6.3.3 Measurement Discussion.....................89

CHAPTER 7 Conclusions and Future Works...............91
7.1 Conclusions................................91
7.2 Future Works...............................92

Bibliography.............................................93

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