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研究生:黃至鴻
研究生(外文):Hwang, Chih-Hong
論文名稱:具立體通道之矽奈米級金氧半場效應電晶體本質參數擾動之研究
論文名稱(外文):Intrinsic Parameter Fluctuation in Nanoscale MOSFET with Vertical Silicon Channels
指導教授:李義明李義明引用關係
指導教授(外文):Li, Yiming
學位類別:博士
校院名稱:國立交通大學
系所名稱:電信工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:98
語文別:英文
論文頁數:221
中文關鍵詞:本質參數擾動奈米級電晶體多閘極電晶體模擬
外文關鍵詞:Intrinsic Parameter FluctuationNanoscale TransistorVertical Channel TransistorModeling
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延續摩爾定律而獲得高性能矽晶片以及高密度元件之觀點,新材料、新製程與新結構的開發是半導體製造上繼續微縮元件的尺寸最有效的策略方案;其中,16 奈米之後電晶體結構的改變儼然已成為非常前瞻與重要的趨勢,因此研究隨機摻雜問題與製程變異在多重閘極場效電晶體特性之影響已為重要且急迫之課題之一。因此本論文發展了三維度元件電路模擬技術使用等效原子層級離散摻雜暨量子傳輸方程的大尺度統計運算方法,並成功地分析16 奈米立體矽場效應電晶體特性之擾動由單閘極、雙閘極、三閘極至全閘極電晶體。此研究方法之準確度已成功地以次20 奈米矽場效應電晶體特性之實驗驗證。相較於單閘極電晶體,臨界電壓擾動在雙閘極、三閘極至全閘極分別被壓抑2.2、3.3 與4 倍,壓抑的原理及物理特性均有探討。此外,近來金屬閘極與高介電係數材料的使用已成為奈米電晶體元件開發之重要課題,但金屬閘極的使用將因金屬材料本身結晶顆粒的大小與方向帶來另外的擾動來源,因此本論文發展蒙地卡羅方法廣泛的分析閘極功函數擾動、離散摻雜擾動與製程變異在多重閘極場效電晶體特性暨其電路之影響,發現閘極功函數擾動對於金屬閘極電晶體尤其是p-type 元件之重大影響,此論文結果對於電晶體擾動壓抑之推估以及下世代電晶體特性擾動分析極有助益。
Gate-length scaling is still the most effective way to continue Moore’s Law for transistor density increase and chip performance enhancement. Accompanied with complementary metal-oxide-semiconductor (CMOS) technology advanced to 45-nm node in production, further scaling down to sub-20 nm and even beyond has been widely noticed encountering much more challenges at short channel control than previous generations. The worsened short channel control of nanoscale transistor not only increases standby power dissipation, but also enlarges electrical characteristic fluctuations, such as the deviation of threshold voltage, drive current, mismatch, and so on. The fluctuation budget has to be controlled even tighter due to doubly increased transistor number along with technology node moving ahead. Moreover, the fluctuation is intrinsically increased with the scaling of transistor feature size, even not considering worsened short channel control. This thesis describes the intrinsic parameter fluctuations in vertical-channel devices from planar transistor to double gate, tri-gate, omega fin-type field effect transistors (FinFETs) and nanowire FinFETs through experimental validated three-dimension device simulation and characterization. The implications of device variability in nanoscale transistor circuits are advanced. The extensive study assesses the fluctuations on device and circuit reliability, which can in turn be used to optimize nanoscale MOSFET and circuits. Full realization of the benefit of nanoscale transistor therefore requires development and optimization of new device materials, structures, and technologies to keep transistor performance and reliability.
Abstract v
Acknowledgments vii
List of Tables xiii
List of Figures xv

1 Introduction 1
1.1 Toward Nanoscale Transistor Era 1
1.2 Vertical Channel Transistor Architecture 5
1.2.1 FinFET Process Steps 7
1.2.2 Process Simulation Using TCAD 8
1.3 Current Research Status and Motivation 10
1.4 Outline 15

2 Device Model and Numerical Methods 17
2.1 The Quantum-Mechanical Corrected Transport Equations 17
2.1.1 The Density-Gradient Equations 17
2.1.2 The Mobility Model 21
2.2 The Numerical Simulation Methods 22
2.2.1 The Gummel Decoupling Method 22
2.2.2 The Adaptive Finite Volume Method 25
2.2.3 The Monotone Iterative Method 28
2.3 A 25-nm FinFET Simulation and Calibration 30
2.4 Summary 45

3 Simulation of Intrinsic Parameter Fluctuation 47
3.1 Process Variation Effect 48
3.2 Random-Dopant-Induced Characteristics Fluctuation 50
3.2.1 Discrete Dopant Generation Method 52
3.2.2 Kinetic Monte Carlo Simulation 56
3.3 Workfunction fluctuation 59
3.4 Calibration and Verification 67
3.5 Summary 75

4 Random-Dopant-Induced Characteristics Fluctuation in Vertical-Channel Devices 77
4.1 Bulk Fin-Type Field Effect Transistors 78
4.1.1 Roll-Off Characteristics 79
4.1.2 Comparison with Planar MOSFETs with High-‧ Dielectrics 93
4.2 Silicon-on-Insulator Transistors 105
4.3 Summary 126

5 Intrinsic Parameter Fluctuation in Fin-Typed Field Effect Transistors 128
5.1 DC Characteristic Fluctuation 129
5.2 AC Characteristic Fluctuation 134
5.3 Summary 143

6 Implication of Device Variability in Circuits 145
6.1 The Coupled Device-Circuit Simulation Technique 146
6.2 Digital Circuits 151
6.3 Analog/High-Frequency Circuits 168
6.4 Summary 179

7 Conclusions and FutureWork 181
7.1 Conclusion of This Study 181
7.2 Suggestions on the Suppression Approaches 182
7.2.1 Vertical Doping Profile Engineering 182
7.2.2 Inverse Lateral Asymmetry Doping Profile 188
7.3 Suggestions on the Future Work 191

References 194
Appendix A
VITA 219
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