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S. Y. Huang, ”Diagnosis of Byzantine Open-Segment Faults”, Proc. Asian Test Symp. (ATS), pp. 248-253, Nov. 2002. W. Zou,W. T. Cheng and S. M. Reddy, ”Interconnect open defect diagnosis with physical information”, Proc. Asian Test Symp. (ATS), pp. 203-209, Nov. 2006. X. Yu and R. D. Blanton, ”Multiple defect diagnosis using no assumption on failing pattern characteristics”, Proc. Design Automation Conf. (DAC), pp. 361-366, Jun. 2008. W. C. Tam, O. Poku and R. D. Blanton, ”Automated failure population creation for validating integrated circuit diagnosis methods”, Proc. Design Automation Conf. (DAC), pp. 708-713, Jul. 2009. Y. C. Lin and K. T. Cheng, ”Multiple-fault diagnosis based on single-fault activation and single-output observation”, Proc. Design, Automation and Test in Europe Conf. (DATE), pp. 1-6, Mar. 2006. C. F. Hawkins, J. M. Soden, A. W. Righter and F. J. Ferguson, ”Defect classes - An overdue paradigm for CMOS IC testing”, Proc. Int’l Test Conf. (ITC), pp. 413-425, Oct. 1994. T. Bartenstein, D. Heaberlin, L. Huisman and D. Sliwinski, ”Diagnosing combinational logic designs using single location at-a-time (SLAT) paradigm”, Proc. Int’l Test Conf. (ITC), pp. 287-296, Oct. 2001. J. B. Liu, A. Veneris and H. Takahashi, ”Incremental diagnosis of multiple openinterconnects”, Proc. Int’l Test Conf. (ITC), pp. 1085-1092, Oct. 2002. Y. Sato, I. Yamazaki, H. Yamanaka, T. Ikeda and M. Takakura, ”A persistent diagnostic technique for unstable defects”, Proc. Int’l Test Conf. (ITC), pp. 242-249, Oct. 2002. X. Lin and J. Rajski, ”Test generation for interconnect opens”, Proc. Int’l Testing Conf. (ITC), pp. 1-7, Oct. 2008. J. B. Liu, A. Veneris and M. S. Abadir, ”Efficient and exact diagnosis of multiple stuck-at faults”, Proc. Latin-American Test Workshop (LATW), Feb. 2002. S. Venkataraman and S. B. Drummonds, ”A technique for logic fault diagnosis of interconnect open defects”, Proc. VLSI Test Symp. (VTS), pp. 313-318, Apr. 2000. X. Fan, W. Moore, C. Hora, M. Konijnenburg and G. Gronthoud, ”A gate-level method for transistor-level bridging fault diagnosis”, Proc. VLSI Test Symp. (VTS), pp. 266-271, Apr. 2006. S. Spinner, I. Polian, P. Engelke, B. Becker, ”Automatic test pattern generation for interconnect open defects”, Proc. of VLSI Test Symp. (VTS), pp. 181-186, Apr. 2008. Z. Wang, M. M. Sadowska, K. H. Tsai and J. Rajski, ”Multiple fault diagnosis using n-defection tests”, Proc. Int’l Conf. Computer Design (ICCD), pp. 198-201, Oct. 2003. H. Sue, C. Di and J. A. G. Jess, ”Probability analysis for CMOS floating gate faults,” Proc. Europe Design Test Conf. (EDTC), pp. 443-448, Feb. 1994. C. Y. Kao, C. H. Liao, and H. P. Wen, ”An ILP-based diagnosis framework for multiple open defects”, Proc. Int’l Microprocessor Testing and Verification Workshop (MTV), pp. 69-72 Dec. 2009. X. Wen, H. Tamamoto, K. K. Saluja and K. Kinoshita, ”Fault diagnosis for physical defects of unknown behaviors”, IEEE Asian Test Symp. (ATS), pp. 236-241, Nov. 2003. Y. C. Lin, F. Lu, and K. T. Cheng, ”Multiple-fault diagnosis based on adaptive diagnostic test pattern generation”, IEEE Tran. CAD of Integrated Circuits and Systems (TCAD), vol. 26, pp. 932-942, May 2007. S. Y. Huang, ”A symbolic inject-and-evaluate paradigm for byzantine fault diagnosis”, Jour. Electronic Testing: Theory and Application (JETTA), vol. 19, pp. 161-172, Oct. 2003. Y. Takamatsu,T. Seiyama, H. Takahashi,Y. Higami, and K. Yamazaki, ”On the fault diagnosis in the presence of unknown fault models using pass/fail information”, Int’l Symp. Circuits and Systems (ISCAS) pp. 2987-2990, Vol. 3, May. 2005. M. Renovell and G. Cambon, ”Electrical analysis and modeling of floating-gate fault”, IEEE Tran. CAD of Integrated Circuits and Systems (TCAD), pp. 1450-1458, vol. 11, Nov. 1992. The TAMU Website, http://dropzone.tamu.edu/ xiang/iscas.html R. Rodriguez-Montanes, D. Arumi, S. Einchenberger, C. Hora, B. Kruseman and M. Lousberg, ”Diagnosis of Full Open Defects in Interconeecting Lines”, Proc. VLSI Test Symp. (VTS), pp. 158-166, May. 2007. Z.Wang, M. Marek-Sadowska, K.-H. Tsai and J. Rajski, ”Analysis and Methodology for Multiple-Fault Diagnosis”, IEEE Tran. CAD of Integrated Circuits and Systems (TCAD), pp. 559-575, vol.25, Mar. 2006. S. Hillebrecht, I. Polian, P. Engelke, B. Becker, M. Keim and W.-T. Cheng, ”Extraction, Simulation adn Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model”, Proc. Int’l Testing Conf. (ITC), pp. 1-10, Oct. 2008. S. M. Reddy, I. Pomeranz, H. Tang, S. Kajihara and K. Kinoshita, ”On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout”, Proc. Int’l Testing Conf. (ITC), pp. 83-89, Oct. 2002.
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