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研究生:高振源
研究生(外文):Kao, Chen-Yuan
論文名稱:應用於多重拜占庭開放線段缺陷上以整數線性規劃為基礎的錯誤診斷方法設計
論文名稱(外文):Integer-Linear-Programming (ILP) Based Diagnosis of Multiple Byzantine Open-Segment Defects
指導教授:溫宏斌
指導教授(外文):Wen, Hung-Ping
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:47
中文關鍵詞:拜占庭效應診斷開放線段
外文關鍵詞:Byzantine effectDiagnosisOpen defect
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開放線段缺陷所表現的錯誤決定於拜占庭效應和實體電路的繞線情形。拜占庭效應使得錯誤表現會依據模組和實體電路的資訊而變化,所以傳統的自動模組產生器在確保缺陷錯誤的啟動與傳遞上顯得相當困難。這篇論文提供了三階段的診斷方法設計用於自動尋找開放線段的組合。路徑回溯技巧幫助我們從錯誤模組中擷取所有可能存在開放線段的位置。整數線性規劃工具則根據可能的錯誤點和模擬結果列舉所有線路錯誤組合。最後,錯誤模擬則刪除不符合的組合幫助我們找到實際符合錯誤效應的線段組合。對ISCAS85電路注入多重開放線段缺陷的實驗結果顯示出此方法的分辨率相當有效,且可以產生小於9組的診斷率高的錯誤組合。
The faulty responses of an open defect are determined by the Byzantine effect and the physical routing. The Byzantine effect makes such faulty behaviors non-deterministic and depends upon both the pattern and physical information. Therefore, traditional ATPG has difficulty on its fault activation and propagation. This paper proposes a three-stage diagnosis approach of finding combinations of open-segment defects automatically. Path tracing technique helps extract all candidate fault sites from error outputs of failing patterns. An ILP solver enumerates all net fault by considering fault candidates and simulation responses. Last, fault simulation identifies true open-segment faults by pruning false cases. Experimental results shows the resolution of the proposed approach is high and only generates <9 faults with good diagnosability on all ISCAS 85 circuits under multiple injected open-segment defects.
1 Introduction 1
2 Previous Researches 6
3 Fault Model of Open Segments 10
4 Three-Stage Integet-Linear-Programming (ILP) Based Diagnosis 14
4.1 Net Fault Identification 16
4.2 N-net Fault Generation 17
4.3 N-segment Fault Composition 22
4.4 Performance Comparison of Applied Constraints 23
5 Experimental Results 25
5.1 Results under Random Pattern 26
5.2 Results under 5-detect Pattern 27
5.3 Diagnosability and Resolution Comparison 33
6 Conclusion 43
Bibliography 45
S. Y. Huang, ”Diagnosis of Byzantine Open-Segment Faults”, Proc. Asian Test Symp.
(ATS), pp. 248-253, Nov. 2002.
W. Zou,W. T. Cheng and S. M. Reddy, ”Interconnect open defect diagnosis with physical
information”, Proc. Asian Test Symp. (ATS), pp. 203-209, Nov. 2006.
X. Yu and R. D. Blanton, ”Multiple defect diagnosis using no assumption on failing
pattern characteristics”, Proc. Design Automation Conf. (DAC), pp. 361-366, Jun.
2008.
W. C. Tam, O. Poku and R. D. Blanton, ”Automated failure population creation for validating
integrated circuit diagnosis methods”, Proc. Design Automation Conf. (DAC),
pp. 708-713, Jul. 2009.
Y. C. Lin and K. T. Cheng, ”Multiple-fault diagnosis based on single-fault activation
and single-output observation”, Proc. Design, Automation and Test in Europe Conf.
(DATE), pp. 1-6, Mar. 2006.
C. F. Hawkins, J. M. Soden, A. W. Righter and F. J. Ferguson, ”Defect classes - An
overdue paradigm for CMOS IC testing”, Proc. Int’l Test Conf. (ITC), pp. 413-425,
Oct. 1994.
T. Bartenstein, D. Heaberlin, L. Huisman and D. Sliwinski, ”Diagnosing combinational
logic designs using single location at-a-time (SLAT) paradigm”, Proc. Int’l Test Conf.
(ITC), pp. 287-296, Oct. 2001.
J. B. Liu, A. Veneris and H. Takahashi, ”Incremental diagnosis of multiple openinterconnects”,
Proc. Int’l Test Conf. (ITC), pp. 1085-1092, Oct. 2002.
Y. Sato, I. Yamazaki, H. Yamanaka, T. Ikeda and M. Takakura, ”A persistent diagnostic
technique for unstable defects”, Proc. Int’l Test Conf. (ITC), pp. 242-249, Oct. 2002.
X. Lin and J. Rajski, ”Test generation for interconnect opens”, Proc. Int’l Testing
Conf. (ITC), pp. 1-7, Oct. 2008.
J. B. Liu, A. Veneris and M. S. Abadir, ”Efficient and exact diagnosis of multiple
stuck-at faults”, Proc. Latin-American Test Workshop (LATW), Feb. 2002.
S. Venkataraman and S. B. Drummonds, ”A technique for logic fault diagnosis of
interconnect open defects”, Proc. VLSI Test Symp. (VTS), pp. 313-318, Apr. 2000.
X. Fan, W. Moore, C. Hora, M. Konijnenburg and G. Gronthoud, ”A gate-level
method for transistor-level bridging fault diagnosis”, Proc. VLSI Test Symp. (VTS),
pp. 266-271, Apr. 2006.
S. Spinner, I. Polian, P. Engelke, B. Becker, ”Automatic test pattern generation for
interconnect open defects”, Proc. of VLSI Test Symp. (VTS), pp. 181-186, Apr. 2008.
Z. Wang, M. M. Sadowska, K. H. Tsai and J. Rajski, ”Multiple fault diagnosis using
n-defection tests”, Proc. Int’l Conf. Computer Design (ICCD), pp. 198-201, Oct. 2003.
H. Sue, C. Di and J. A. G. Jess, ”Probability analysis for CMOS floating gate faults,”
Proc. Europe Design Test Conf. (EDTC), pp. 443-448, Feb. 1994.
C. Y. Kao, C. H. Liao, and H. P. Wen, ”An ILP-based diagnosis framework for
multiple open defects”, Proc. Int’l Microprocessor Testing and Verification Workshop
(MTV), pp. 69-72 Dec. 2009.
X. Wen, H. Tamamoto, K. K. Saluja and K. Kinoshita, ”Fault diagnosis for physical
defects of unknown behaviors”, IEEE Asian Test Symp. (ATS), pp. 236-241, Nov.
2003.
Y. C. Lin, F. Lu, and K. T. Cheng, ”Multiple-fault diagnosis based on adaptive diagnostic
test pattern generation”, IEEE Tran. CAD of Integrated Circuits and Systems
(TCAD), vol. 26, pp. 932-942, May 2007.
S. Y. Huang, ”A symbolic inject-and-evaluate paradigm for byzantine fault diagnosis”,
Jour. Electronic Testing: Theory and Application (JETTA), vol. 19, pp. 161-172,
Oct. 2003.
Y. Takamatsu,T. Seiyama, H. Takahashi,Y. Higami, and K. Yamazaki, ”On the fault
diagnosis in the presence of unknown fault models using pass/fail information”, Int’l
Symp. Circuits and Systems (ISCAS) pp. 2987-2990, Vol. 3, May. 2005.
M. Renovell and G. Cambon, ”Electrical analysis and modeling of floating-gate
fault”, IEEE Tran. CAD of Integrated Circuits and Systems (TCAD), pp. 1450-1458,
vol. 11, Nov. 1992.
The TAMU Website, http://dropzone.tamu.edu/ xiang/iscas.html
R. Rodriguez-Montanes, D. Arumi, S. Einchenberger, C. Hora, B. Kruseman and M.
Lousberg, ”Diagnosis of Full Open Defects in Interconeecting Lines”, Proc. VLSI Test
Symp. (VTS), pp. 158-166, May. 2007.
Z.Wang, M. Marek-Sadowska, K.-H. Tsai and J. Rajski, ”Analysis and Methodology
for Multiple-Fault Diagnosis”, IEEE Tran. CAD of Integrated Circuits and Systems
(TCAD), pp. 559-575, vol.25, Mar. 2006.
S. Hillebrecht, I. Polian, P. Engelke, B. Becker, M. Keim and W.-T. Cheng, ”Extraction,
Simulation adn Test Generation for Interconnect Open Defects Based on Enhanced
Aggressor-Victim Model”, Proc. Int’l Testing Conf. (ITC), pp. 1-10, Oct. 2008.
S. M. Reddy, I. Pomeranz, H. Tang, S. Kajihara and K. Kinoshita, ”On Testing
of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large
Fanout”, Proc. Int’l Testing Conf. (ITC), pp. 83-89, Oct. 2002.
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