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研究生:黃景裕
研究生(外文):Huang, Ching-Yu
論文名稱:針對半導體製程金屬層良率提昇研究
論文名稱(外文):Metal layer yield improvement for semiconductor process
指導教授:張翼張翼引用關係
指導教授(外文):Chang, Yi Edward
學位類別:碩士
校院名稱:國立交通大學
系所名稱:工學院碩士在職專班半導體材料與製程設備組
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:56
中文關鍵詞:半導體錐狀金屬良率
外文關鍵詞:semiconductorCoMetal taperYield
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矽晶圓成熟的技術與低廉的價格,造就了蓬勃的消費性電子產業,但隨著元件線寬不斷縮小下,半導體製程技術越趨困難,已無法用一致化的程式來面對多元化的產品,因此需要更多的儀器分析與實驗,來為每個產品進行微調!
本公司的產品便深受其害,良率無法達到量產的標準,於是便利用了SEM與SIMS分析,找出下列的問題:
1. 接觸窗與下方的金屬對準不良
2. 鈷金屬矽化物出現缺陷與阻值過高
3. 接觸窗蝕刻程式無法共用,有些產品蝕刻不足導致短路,有些蝕刻過頭導致電化學效應,讓金屬層下方的接觸窗遭到侵蝕
針對上述的問題我們進行了一連串的實驗與分析,亦找到一些方法來改善這個現象,下列是我們採取的方法:
1. 使用曝光較為精準的Scanner 機台來取代Stepper。
2. 使用新的錐狀金屬蝕刻程式,將金屬層蝕刻為錐狀,可以完整覆蓋下方的接觸窗
3. 使用PE SiH4機台來取代LPTEOS機台,讓鈷金屬矽化物不會有缺陷的產生。
4. 改變鈷金屬矽化物的回火溫度,讓其阻值更低。
5. 改變金屬窗蝕刻程式,讓不同厚度的產品都可使用,不致於讓厚度較厚的產品沒有蝕刻開來,而造成短路,也不會讓厚度較薄的產品蝕刻過頭,導致金屬層下方的接觸窗掏空。
針對不同的產品設計與特性,便會有不同的改善良率的方法,讓我們不斷的努力研究,讓電子產品更加進步與便宜。

The mature technology and inexpensive price of Silicon wafer makes electrical consumer industrial become popular. But the technology of semiconductor process becomes more difficult with the device width becomes smaller. Therefore, we can’t use the same recipe on various products. We need more instruments for analysis and experiments. And use the results to optimize the recipe for each product.
Our company’s product has suffered this issue and yield can’t meet the criteria of production. Hence, we used SEM and SIMS to analyze and found below issues.
1. Metal via and under layer metal line un-landing
2. Defect occurred and resistance too high on cobalt silicide
3. We can’t use the same metal via etching recipe for all products. Some products may encounter short issue due to etch not enough. Some products may induce electrochemistry effect with over etch. And this caused the metal via under metal be damaged.
We did a series of experiments and analysis for above issues and found some methods to improve them. The methods are listed as below:
1. Use scanner which has more accurate exposure ability instead stepper.
2. Use taper metal etching recipe and this can fully cover the metal via under metal layer.
3. Use PE SiH4 tool to replace LPTEOS tool and this can make defect not occur of cobalt silicide.
4. Change anneal temperature of cobalt silicide to reduce resistance.
5. Change metal etching recipe to let the products with different metal thickness can use the same recipe. And it won’t cause short issue when metal is thicker. When metal is thinner, it won’t cause metal via under metal layer be damaged.
For diverse product designs and characteristics, it will have different methods to improve yield. Let us keep putting efforts on research and make electrical products more progress and cheaper.

中文提要 ………………………………………………………… iii
英文提要 ………………………………………………………… iv
誌謝 ………………………………………………………… v
目錄 ………………………………………………………… vi
表目錄 ………………………………………………………… vii
圖目錄 ………………………………………………………… viii
一、 緒 論 ………………………………………………… 1
1.1 前言…………………………………………………… 1
1.2 研究動機與目的……………………………………… 2
二、 半導體製程…………………………………………… 3
2.1 半導體製程簡介……………………………………… 3
2.2 材料分析機台簡介…………………………………… 10
2.2.1 二次離子質譜儀 SIMS ……………………………… 10
2.2.2 掃描式電子顯微鏡…………………………………… 13
三、 產品良率提昇與驗證………………………………… 16
3.1 產品低良率的現況…………………………………… 16
3.2 使用分析儀器SEM & SIMS來找尋失效原因 ………… 18
3.3 針對對準不良進行分析與改善……………………… 20
3.4 尋找其他失效原因(I)-改變金屬矽化物沈積方式
與回火溫度…………………………………………… 22
3.5 尋找其他失效原因(II)-鈷金屬矽化物沈積搭配曝
光機台的實驗………………………………………… 29
3.6 尋找其他失效原因(III)-錐狀金屬蝕刻………… 35
3.7 M1錐狀金屬蝕刻的程式最佳化 …………………… 41
3.8 M2~M5錐狀金屬蝕刻的程式最佳化 ………………… 44
3.9 產品程式最佳化……………………………………… 46
3.10 產品平均失效時間驗證……………………………… 52
四、 結論與展望…………………………………………… 54
參考文獻 ………………………………………………………… 55
[1] Randal S. Collica, Member, IEEE, Jill P. Card, Member, IEEE, and William Martin, "RAM Bitmap Shape Recognition and Sorting Using Neural Networks"
[2] J. Khare, D. B. I. Feltham, and W. Maly, "Accurate estimations of defect-related yield loss in reconfigurable VLSI circuits," IEEE J Solid-State Circuits, vol. 28, no. 2, pp. 146-156, Feb. 1993.
[3] S. Kikuda, H. Miyamoto, S. Mori, M. Niiro, and M.Yamada, "Optimized redundancy selection based on failure-related yield model for 64-Mbit DRAM and beyond," IEEE J. Solid-State Circuits vol. 26, no. 11, pp. 1550-1555. Nov. 1991.
[4] R. Mayer, S. Lopez, and D. Bakker, "Correlating defects to bit map failures using automated patterned wafer inspection systems," presented at the UltraClean Manufacturing Symposium, Feb. 1992
[5] C. H. Strapper, "On yield, fault distributions, and clustering of particles," IBM J. Res. Dev., vol. 30, no. 3, pp. 326-338, May 1986.
[6] R.G. Heideman1, A. Melloni2, M. Hoekman1, A. Borreman1, A. Leinse1 and F.Morichetti2 "Low loss, high contrast optical waveguides based on CMOS compatible LPCVD processing: technology andexperimental results"Proceedings Symposium IEEE/LEOS Benelux Chapter, 2005, Mons
[7] T. Hattori, J. Ruzyllo, R. Novak, P. Mertens, P. Besson, "Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing 11" pp. 353-357
[8] Kyunghae Kim, Suresh Kumar Dhungel, Utpal Gangopadhyay, Jinsu Yoo, Choi Won Seoka and Junsin Yi "A novel approach for co-firing optimization in RTP for the fabrication of large area mc-Si solar cell"2006
[9] Chenming Hu "Gate Oxide Scaling Limits and Projection"IEEE Trans. Electron Dev., 1996
[10] S Fang, JP McVittie , "Thin-oxide damage from gate charging during plasma processing"- IEEE Electron Device Letters, 1992
[11] S. V. Hattangady, H. Niimi, and G. Lucovsky "Controlled nitrogen incorporation at the gate oxide surface"Appl. Phys. Lett. 66, 3495 (1995)
[12] Hewlett-Packard Development Company, L.P. "System and method for generating a shmoo plot by avoiding testing in failing regions November" 16, 2004
[13] N.Ranganathan, Liao Ebin, Linn Linn, Lee Wen Sheng Vincent, O.K.Navas,V.Kripesh and N.Balasubramanian, "Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon Interconnection" IEEE 2008

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