臺灣博碩士論文加值系統

TFT-LCD驅動電路有兩種：源極驅動器和閘極驅動器。本論文的目標在於薄膜電晶體平面液晶顯示器(TFT-LCD)之閘極驅動晶片設計。此系統主要電路包含移位暫存器、升壓電路、輸出緩衝器。
我們提出一個驅動高負載的TFT-LCD閘極驅動器之全擺幅輸出數位緩衝器，利用單一電容提升技術(SCB)來提升驅動能力，是使用0.35 m製程技術以及使用Hspice模擬。結果顯示在驅動TFT-LCD UXGA規格的掃瞄線面板下，在操作電壓5 V時的延遲時間皆小於2.8 μs，功率消耗只有1.5 mW。

The driver circuits of TFT-LCD are composed of two parts, the source driver and the gate driver. In this thesis, we focus on the design of gate driver circuits for TFT-LCD display. The architecture consists of the following major blocks, i.e., a shift register, level shifter, and output buffer.
We propose a high-speed full-swing output digital driver for heavy-loads TFT-LCD gate drivers. High driving capability is achieved by using a Single Capacitor Bootstrapped (SCB) technique. The proposed technique the Capacitors numbers and thus can expect to have lower power consumption and reduce delay time. The gate driver has been implemented in TSMC 2P4M 0.35 m CMOS technology and Hspice. Measured results indicate that the delay time is within 2.8 μs for the scan-line load modeling of TFT-LCD UXQA panel in a 5 V supply voltage. The obtained average power is 1.5 mW.

摘要 i
ABSTRACT ii
謝誌 iii
TABLE OF CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES viii

CHAPTER 1 INTRODUCTION 1
1-1 Motivation 1
1-2 Organization of the Thesis 5
CHAPTER 2 TFT-LCD FUNDAMENTALS 6
2-1 Liquid Crystals 6
2-2 LCD Panel Structure 9
2-3 Driving Principle 11
2-4 Gamma Correction 12
2-5 Basic Functions of TFT-LCD Driver 14
2-6 SourceDriver 14
2-7 Direct-Bootstrap Techniques 15
CHAPTER 3 DESIGN OF GATE DRIVER 18
3-1 shift register 19
3-2 Level shifter 21
3-3 Digital Output Buffer 22
CHAPTER 4 EXPERIMENTAL RESULTS 27
4-1 Simulation and Measurement Results 27
4-2 Comparison 32
CHAPTER 5 CONCLUSIONS 35
REFERENCES 36

LIST OF FITURES
Fig. 1.1 Block diagram showing the driving of an LCD panel 4
Fig. 1.2 Signals on the data line versus the waveforms on the near and far ends of the scan line for a large size TFT-LCD panel 4
Fig. 2.1 Phases of LC materials versus temperature 8
Fig. 2.2 Basic theory of liquid crystal display 8
Fig. 2.3 The vertical structure of LCD panel 10
Fig. 2.4 Pixel is controlled by appropriate pixel voltage VLC 10
Fig. 2.5 The effective circuit of each sub-pixel 11
Fig. 2.6 Diagrams of inversion method. (a) Frame Inversion (b) Row Inversion (c) Column Inversion (d) Dot Inversion 12
Fig. 2.7 Transparency-to-voltage curve 13
Fig. 2.8 Block diagram of a source driver 15
Fig. 2.9 Circuit diagram of the DB buffer 17
Fig. 2.10 Circuit diagram of the CDUB buffer 17
Fig. 3.1 The block diagram of gate driver 19
Fig. 3.2 Shift register of the gate driver 20
Fig. 3.3 Timing diagram of a shift register 20
Fig. 3.4 Schematic of the D-Flip-Flop 21
Fig. 3.5 Schematic of the level shifter 22
Fig. 3.6 Schematic of the inverter 24
Fig. 3.7 Schematic of the proposed SCB driver 24
Fig. 3.8 Equivalent circuits of the SCB driver during the pull-up operation, (a) at time prior to pull-up transient and (b) at time after input ramp-down period 25
Fig. 3.9 The internal voltage waveforms of nodes Vout, 1, and 2 when input signal is 5 V square waveform with the supply voltage of 5 V 26
Fig. 4.1 Pulse-wave responses of the SCB scan-line driver with 5 V voltage swing for a load of modeled LCD scan-line 29
Fig. 4.2 Transient waveforms at temperatures 0℃, 25℃ and 85℃ 29
Fig. 4.3 Transient waveforms with supply voltages of 5 ± 10% V 30
Fig. 4.4 Transient waveforms of the three channels of gate driver at nodes clk, in, rest, out1, out2, and out3 30
Fig. 4.5 Layout of the three channel gate driver, the effect size is 1.13μm× 0.9μm 31
Fig. 4.6 Gate driver IC for TFT-LCD driver circuit 31
Fig. 4.7 Power×delay versus output load capacitance of the SCB、DB and CDUB buffer 33
Fig. 4.8 Power versus supply voltage of the SCB、DB and CDUB
Driver 34

LIST OF TABLES
Table I Design rules of 17-in. SXGA TFT 3
Table II Timing specification of video signal. 3

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