|
[1] Jinn-Shyan Wang, Ching-Rong Chang, and Chingwei Yeh, “Analysis and Design of High-Speed and Low-Power CMOS PLAs,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 8, pp. 1250-1262, Aug. 2001.
[2] Reza Molavi, Shahriar Mirabbasi, and Resve Saleh, “A High-Speed Low-Energy Dynamic PLA Using an Input-Isolation Scheme,” IEEE International Symposium on Circuit and Systems, pp. 2885-2888, Proc. of ISCAS 2006.
[3] Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, and Chia-Hsiung Kao, “A Low-Power and High-Speed Dynamic PLA Circuit Configuration for Single-Clock CMOS,” IEEE Transactions on Circuit and Systems, Vol. 46, No. 7, pp. 857–861, July 1999.
[4] Tzyy-Kuen Tien, Chin-Shen Tsai, Shih-Chieh Chang, and Chingwei Yeh, “Power Minimization for Dynamic PLAs,” IEEE Transaction on VLSI Systems, Vol. 14, No. 6, pp. 616–624, June 2006.
[5] Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, and Ying-Pei Chen, “Design of an Inter-plane Circuit for Clocked PLAs,” IEEE International Symposium on Circuit and Systems, Vol. 14, No. 4, pp. 281-284, Proc. of ISCAS 2000.
[6] Yong-B. Dhong and C.-P. Tsang, “High Speed CMOS POS PLA using Predischarged OR Array and Charge Sharing AND Array,” IEEE Transactions on Circuit and Systems, Vol. 39, No. 8, Aug. 1992.
[7] N. Weste and K. Eshrahian, Principles of CMOS VLSI Design−A System Perspective, ed. 1, Addison-Wesley, 1985.
[8] Byung-Do Yang and Lee-Sup Kim, “A Low-Power Charge-Recycling ROM Architecture,” IEEE Transaction on VLSI Systems, Vol. 11, No. 4, pp. 590-600, Aug. 2003.
[9] Byung-Do Yang and Lee-Sup Kim, “A Low-Power ROM Using Single Charge-Sharing Capacitor and Hierarchical Bit Line,” IEEE Transaction on VLSI Systems, Vol. 14, No. 4, pp. 313-322, Apr. 2006.
[10] Byung-Do Yang and Lee-Sup Kim, “A Low-Power Charge Sharing ROM Using Dummy Bit Lines,” IEEE International Symposium on Circuit and Systems, Vol. 5, pp. 377-380, Proc. of ISCAS 2003.
[11] Muhammad-M. Khellah and Mohamed-I. Elmasry, “Low-Power Design of High-Capacitive CMOS Circuits Using a New Charge Sharing Scheme,” IEEE International Solid-State Circuits Conference, pp. 286-287, Proc. of ISSCC 1999.
[12] Keejong Kim, Hamid Mahmoodi and Kaushik Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, pp. 446-459, Feb. 2008.
[13] Ehsan Pakbaznia, Farzan Fallah and Massoud Pedram, “Sizing and Placement of Charge Recycling Transistors in MTCMOS Circuits,” IEEE/ACM International Conference on Computer-Aided Design, pp. 791-796, Proc. of ICCAD 2007.
[14] Zhiyu Liu and Volkan Kursun, “Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS,” 8th International Symposium on Quality Electronic Design, pp. 239-244, Proc. of ISQED 2007.
[15] Jose-C. Garcia, Juan-A. Montiel–Nelson and Saeid Nooshabadi, “High Performance CMOS 2–Input NAND Based on Low–Race Split–Level Charge–Recycling Pass–Transistor Logic,” 12th Euromicro Conference on Digital System Design / Architectures, Methods and Tools, pp. 593-596, Proc. of DSD 2009.
[16] Z. Louis, “Compact ROM matrix,” U.S. patent US5917224, European patent EP0810665, Japan patent JP10056083.
[17] A. Bellaouar and M. I. Elmasry, Low-power digital VLSI design: Circuits and Systems. Norwood, MA: Kluwer, 1995. [18] Gerard M. Blair, “PLA Design for Single-Clock CMOS,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 8, pp. 1211-1213, Aug. 1992.
[19] Oh J. Kwang-I1, Lee-Sup Kim, “A High Performance Low Power Dynamic PLA with Conditional Evaluation Scheme,” IEEE International Symposium on Circuit and Systems, Vol. 2, pp. 881-884, Proc. of ISCAS 2004.
[20] Muhammad Arsalan and Maitham Shams, “Review of Charge-Sharing Logic Circuits,” Canadian Conference on Electrical and Computer Engineering, Vol. 4, pp. 1919-1922, Proc. of CCECE 2004.
[21] Kee-Jong Kim, Chris H. Kim and Kaushik Roy, “TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique,” Sixth International Symposium on Quality of Electronic Design, pp. 59-64, Proc. of ISQED 2005.
[22] Ilias Bouras, Yiannis Liaperdos and Angela Arapoyanni, “A High Speed Low Power CMOS Clock Driver Using Charge Recycling Technique,” IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 657-660, Proc. of ISCAS, May 2000.
[23] Ehsan Pakbaznia, Farzan Fallah and Massoud Pedram, “Charge Recycling in MTCMOS Circuits: Concept and Analysis,” 43rd ACM/IEEE Design Automation Conference, pp. 97-102, Proc. of DAC, July 2006.
[24] Keejong Kim, Hamid Mahmoodi and Kaushik Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, pp. 446-459, Feb. 2008.
|