在現今晶片製程的進步發展，使得數位電路設計複雜度提升，電路的電晶體數量增加，對整體功率和速度的設計要求也相對提高。數位邏輯設計能使用可程式邏輯陣列電路來實現，而靜態可程式邏輯陣列的運算速度與面積不佳，所以本論文使用動態可程式邏輯陣列電路來設計與分析，由於動態可程式邏輯陣列具有高速度及可預期繞線時間，因此常運用於高效能微處理器設計上。
當製程縮小至深次微米之時，則電路內部導線所產生的寄生電容將會比電晶體本身的寄生電容來的大，又隨著電晶體的密度增加，使導線長度成正比上升，此時電路的特性已經和以往各種電路架構所預期的不同。此篇論文討論的重點為分析先前動態可程式邏輯陣列的架構，並提出各架構的優缺點與提出我們的設計架構，我們針對可程式邏輯陣列電路的內部寄生線電容，來運用設計改良架構來完成高效能運算結果。
本論文提出主要設計為電荷回收技術，運用在可程式邏輯陣列的積項線端與輸入線端上各自寄生電容來達到效果，此回收電路能降低積項線端與輸入線端上充電和放電的電壓擺幅，因此減少功率消耗及加快運算速度，最後電路設計使用台積電0.18微米1P6M CMOS 和0.35微米2P4M CMOS技術製程，而模擬分析比較不同動態可程式邏輯陣列電路，因此本提出方法能達到低功率及高速的效能。

The chip is advancement of manufacturing process in nowadays, it to increase design complication of digital circuit, and the transistor amount to increase in circuit, the requests of the design to power and speed are comparatively higher than before, too. The digital logic design using programmable logic array (PLA) circuit to implementation, and static PLA isn’t desirable on operation speed and chip area. This thesis using dynamic PLA circuit to design and analysis, because of dynamic PLA has high speed and predictable routing delay, and therefore it become popular in designing high performance microprocessors.
In deep-submicron fabricating, the internal wire parasitic capacitance greater than transistor parasitic capacitance in the circuit, and the density increase of transistor, the wire routing length in proportion to increase, at this time, the circuit properties isn’t predictive of prior structure. Therefore, we discuss focus of analysis previous dynamic PLA structure, and presentation advantage and drawback of various structures.
This thesis proposes a method of charge recycling technology of PLA which is implemented by using the parasitic capacitance of product-lines and input-lines. This scheme can reduce voltage swing on product-lines and input-lines to decrease power consumption and speed up operation. The circuit was designed by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm 1P6M CMOS and 0.35-μm 2P4M CMOS technology, and analysis and compare with various dynamic PLA by simulation. Therefore, the proposed scheme can reach to low power and high speed.

CONTENTS

CHINESE ABSTRACT i
ENGLISH ABSTRACT iii
ACKNOWLEDGMENTS v
CONTENTS vi
LIST OF FIGURES viii
LIST OF TABLES x

CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 Organization of the Thesis 3
CHAPTER 2 REVIEW OF DYNAMIC PLA 5
2.1 Analysis about Sources of Power Consumption 5
2.2 Conventional Clock-Delayed Dynamic PLA 6
2.3 Blair’s PLA 11
2.4 Kwang’s PLA 13
2.5 Summary 16
CHAPTER 3 THE CHARGE RECYCLING DYNAMIC PLA 17
3.1 Introduction 17
3.2 The Concept of the Charge Recycling Scheme 18
3.3 The Charge Recycling Circuit using Product-Lines of PLA.19
3.4 The Charge Recycling Circuit using Input-Lines of PLA 22
CHAPTER 4 SIMULATION RESULTS 30
4.1 Simulation Tool 30
4.2 Simulation by TSMC 0.35-μm 2P4M CMOS Technology 31
4.3 Simulation by TSMC 0.18-μm 1P6M CMOS Technology 37
4.4 Chip Layout 39
CHAPTER 5 CONCLUSION 43
REFERENCE 44

LIST OF FIGURES

Figure 1.1 The structure of a two-level dynamic PLA 2
Figure 2.1 The conventional 5×8×4 clock-delayed dynamic PLA 7
Figure 2.2 The critical path circuit of clock-delayed dynamic PLA 8
Figure 2.3 The signal propagation waveforms of clock-delayed dynamic PLA 8
Figure 2.4 The critical path circuit of Blair’s PLA 12
Figure 2.5 The signal propagation waveforms of Blair’s PLA 13
Figure 2.6 The critical path circuit of Kwang’s PLA 14
Figure 2.7 The signal propagation waveforms of Kwang’s PLA 14
Figure 3.1 The concept of charge recycling scheme 19
Figure 3.2 The critical path circuit of proposed charge recycling PLA 20
Figure 3.3 The charge recycling circuit in product-lines 20
Figure 3.4 The signal propagation waveforms of proposed charge recycling PLA 22
Figure 3.5 The charge recycling circuit of conventional PLA 23
Figure 3.6 The signal propagation waveforms of conventional PLA using charge recycling circuit 24
Figure 3.7 The conventional PLA using charge recycling circuit in input-lines 25
Figure 3.8 The charge recycling circuit of Kwang’s PLA 27
Figure 3.9 The signal propagation waveforms of Kwang’s PLA using charge recycling circuit 28
Figure 4.1 The Monte Carlo analysis method 31
Figure 4.2 The pre-simulation waveforms of proposed PLA at 100MHz clock
Frequency 33
Figure 4.3 The pre-simulation output waveforms of various PLA at 100MHz clock frequency 34
Figure 4.4 The pre-simulation waveforms of proposed PLA at 100MHz clock Frequency 38
Figure 4.5 Layout of the p82 circuit used the 0.35-μm technology 39
Figure 4.6 Layout of the propose p82 circuit used the 0.35-μm technology 40
Figure 4.7 Layout of the b12 circuit used the 0.18-μm technology 41
Figure 4.8 Layout of the propose b12 circuit used the 0.18-μm technology 41

LIST OF TABLES

Table 4.1 The parasitic capacitance values in the pre-simulation of PLA 32
Table 4.2 The speed performances of different PLA 32
Table 4.3 The pre-simulation performances comparison results of various PLA 35
Table 4.4 The post-simulation results of power consumption and delay 35
Table 4.5 The post-simulation results of power consumption and delay 36
Table 4.6 The parasitic capacitance values in the pre-simulation of PLA 37
Table 4.7 The pre-simulation results of power consumption and delay 37
Table 4.8 The post-simulation results of power consumption and delay 38
Table 4.9 The core of chip size used the 0.35-μm technology 40
Table 4.10 The core of chip size used the 0.18-μm technology 42

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