臺灣博碩士論文加值系統

在無線通訊系統中為了要防止雜訊的干擾，因此傳送端使用迴旋碼將傳送資料編碼，而接收端則使用維特比演算法進行解碼以修正錯誤位元。但是由於維特比演算法運算複雜，其硬體電路會消耗大量功率，故運用在手持系統中會影響待機時間以及手持系統的溫度，為了要解決這些問題我們必須實現一個低功\率的迴旋碼解碼器。
直觀上若接收到的資料沒有發生錯誤時即不必使用維特比解碼器來修正錯誤，因此我們可以使用一個偵測電路來判斷接收到的資料是不是有受到雜訊的干擾。如果沒有受到雜訊干擾，則只需要一個低成本的解碼器進行解碼，而不需要使用維特比解碼器解碼，只有在訊號受到雜訊干擾時才使用維特比解碼器，因此可以降低接收端解碼器所需要的功率消耗。
除此之外，我們再加入動態調整SMU的方法。在維特比解碼器裡SMU這個模組消耗最多的功率，所以我們以減少SMU的使用為目標。假設我們處理的區段資料受到雜訊干擾的程度較不密集，我們就不需要太強大的解碼能力，因此在SMU裡使用的暫存器就可以減少，然後再配合時脈閘控(clock gating)將未使用暫存器的時脈關閉即可達到低功率的效果。
本論文提出的迴旋碼解碼器電路是使用Artisan TSMC 0.13μm標準元件庫來進行合成與實現。與傳統的維特比解碼器相比，我們提出的電路在SNR為1dB時可以節省百分之二十五的功率消耗，SNR為8dB時節省了將近百分之六十的功率消耗，而其面積也減少約百分之六。由以上的實驗結果可知，本論文所提出的具錯誤偵測及動態調整解碼能力之迴旋碼解碼器可以達到降低功\率消耗的效果。

In wireless communication systems, we may encounter many problems. One of the main issues is noise interference. To overcome the problem, the sender can use the Convolutional coding method to encode the data, and the receiver can utilize the Viterbi algorithm for decoding and correction purposes. Due to the high complexity of the Viterbi algorithm, the VLSI structure of Viterbi decoder will consume large amounts of power, leading the portable devices to short standby time and high operating temperature. In order to solve these problems we have to design a low power decoder.
As a matter of fact, the Viterbi decoder can be actually shutdown when no noise interference exists. As a consequence, we use a detection circuit to determine whether the signal is influenced by noise. If the signal is interfered, we choose the Viterbi decoder to perform the decoding process. Otherwise, we utilize a low cost decoder to lessen the power consumed at the receiver end.
In addition, dynamic adjustment of SMU module is also developed and implemented in the proposed decoder. SMU module consumes the most power in Viterbi decoder. So, our developed and goal is to reduce the usage of SMU module. If noise distribution is not so dense, we don’t have to use high decoding ability to decode section data. Therefore, the registers in SMU can be decreased. Clock gating technique is adopted in this thesis to shutdown these idle registers to reduce the power consumption of SMU.
The proposed decoder has been implemented and synthesized using the Artisan TSMC 0.13μm standard cell library. Compared with the traditional Viterbi decoder, the proposed decoder can achieve 25% and nearly 60% power saving when the SNR is 1dB and 8dB respectively, with 6% area reduction. According to the above experimental results, we can say that the proposed decoder is able to reduce power consumption.

摘要 I
Abstract II
目錄 IV
表目錄.........................................................................................................................VI
圖目錄........................................................................................................................VII
第一章 緒論 ..1
1.1 研究背景........................................................................................................1
1.2 研究動機與方向............................................................................................2
1.3 貢獻................................................................................................................3
1.4 論文組織........................................................................................................4
第二章 相關研究與背景知識 5
2.1 迴旋碼(Convolutional Code)簡介...............................................................5
2.2 維特比演算法(Viterbi Algorithm)簡介.......................................................7
2.3 追溯(Trace Back)與暫存器交換(Register Exchange).............................10
2.4 軟式決策(Soft Decision).............................................................................16
2.5 時脈閘控電路(Clock gating circuit)..........................................................17
2.6 Scarce State Transition(SST).....................................................................19
第三章 具錯誤偵測之迴旋碼解碼 21
3.1 具錯誤偵測之迴旋碼..................................................................................21
3.2 錯誤偵測判斷..............................................................................................23
3.3 解碼範例......................................................................................................24
3.4 偵測功能演算法..........................................................................................25
第四章 動態調整解碼能力 27
4.1 評估解碼能力..............................................................................................27
4.2 動態調整SMU模式...................................................................................28
第五章 硬體架構 31
5.1 傳統維特比硬體架構..................................................................................31
5.2 加-比較-選擇單元正規化電路...................................................................33
5.3 具偵測電路迴旋碼解碼器架構..................................................................35
5.4 具動態調整解碼能力硬體架構..................................................................37
第六章 驗證與實驗數據 40
6.1 矽智產驗證..................................................................................................40
6.2 硬體規格......................................................................................................41
6.3 實驗數據......................................................................................................41
第七章 結論與未來工作 46
7.1 結論..............................................................................................................46
7.2 未來目標......................................................................................................47
參考文獻 48

[1]F. Sun and T. Zhang, “Parallel high-throughput limited search trellis decoder VLSI design, ”IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 13, pp. 1013 – 1022, Oct. 2005.
[2]M.-D. Shieh, T.-P. Wang and D.-W., Yang, “Low-power register-exchange survivor memory architectures for Viterbi decoders,” IET Circuits, Devices & Syst., Vol.3,pp. 83 – 90, Apr. 2009.
[3]J.-S. Han, T.-J. Kim and C. Lee,“High performance Viterbi decoder using modified register exchange methods,” Proc. International Symposium on Circuits and Systems,Vol.3, Sep. 2004., pp.III - 553-6.
[4]D.-J. Lin, C.-C. Lin, C.-L. Chen, H.-C. Chang and C.-Yi Lee, “A Low-Power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length,” International Symposium on VLSI Design, Automation and Test., Jun. 2007. , pp.1 – 4.
[5]C.B. Shung, P.H. Siegel, G. Ungerboeck and H.K. Thapar, “VLSI Architectures for Metric Normalization in the Viterbi Algorithm,” IEEE International Conference on Communications. ICC ''90,, Aug. 1990, pp.1723-1728.
[6]Dae-Il Oh and Sun-Young Hwang, “Design of a Viterbi decoder with low power using minimum-transition traceback scheme,” Electronics Letters, pp.2198 – 2199, Nov. 1996.
[7]Yi-Tse Lai and Kelvin, “An efficient metric normalization architecture for high-speed low-power viterbi decoder,” TENCON 2007, Oct. 2007, pp.1 – 4.
[8]M.-H. Chan, W.-Ta Lee, M.-C. Lin and L.-G. Chen, “IC design of an adaptive Viterbi decoder,” IEEE Trans. Consumer Electronics, Vol. 42, pp.52 - 62, Feb. 1996.
[9]J. J. and C.-y. Tsui,“Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition,” IEEE Trans. Very Large Scale Integration (VLSI) Syst.,Vol.15, pp.1172 – 1176, Oct. 2007.
[10]J. Jin and C.-Y. Tsui,“A Low Power Viterbi Decoder Implementation using Scarce State Transition and Path Pruning Scheme for High Throughput Wireless Applications, ”Proc. International Symposium on Low power Electronics and Design, Oct. 2006, pp. 406 – 411, 2006.
[11]T. Ishitani, K. Tansho, N. Miyahara, S. Kubota and S.Kato,“A scarce-state-transition Viterbi-decoder VLSI for bit error correction, ”IEEE Journal of Solid-State Circuits,Vol. 22, pp. 575 - 582, Aug. 1987.
[12]K. Maharatna, A. Troya, M. Krstic and E. Grass, “On the implementation of a low-power IEEE 802.11a compliant Viterbi decoder,” Proc. of 19th International Conference on VLSI Design., Jan. 2006.
[13]G. Feygin and P.G. Gulak, “Survivor sequence memory management in Viterbi decoders,”Proc. IEEE International Sympoisum on Circuits and Syst., vol.5, Jun. 1991, pp.2967 – 2970.
[14]J.-G Baek, S.-H. Yoon and J.-W. Chong, “Memory efficient pipelined Viterbi decoder with look-ahead trace back, ”IEEE International Conference on Electronics, Circuits and Systems,. Vol.2, 2001, pp.769 – 772.
[15]S. Kubota, S. Kato and T. Ishitani, “Novel Viterbi decoder VLSI implementation and its performance,” IEEE Trans. Commun., Vol.41, pp.1170 - 1178, Aug. 1993.
[16]C.-C. Lin, C.-C. Wu and Chen-Yi Lee, “A low power and high speed Viterbi decoder chip for WLAN applications, ”Proc. 29th European. Solid-State Circuits Conf., sept. 2003, pp.723 – 726
[17]G. Feygin and P. Gulak, “Architectural tradeoffs for survivor sequence memory management in Viterbi decoders,” IEEE Trans. Commun., vol.41, pp.425 – 429, Mar. 1993.
[18]S.L.Haridas, “Design of Viterbi decoder with modified traceback and hybrid register exchange processing, ”Proc. International Conference on Advances in Computing, Communication and Control, 2009, pp. 223-226.
[19]C. Keawsai, K. Sripimanwat and A. Lasakul, “Modified Register Exchange Method of Viterbi Decoder for 3GPP Mobile System, ”The First Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology (ECTI), May 2004.
[20]黃仕吉,“應用於無線通訊系統之低功率迴旋碼解碼器,”碩士論文,國立成功大學資訊工程學系,中華民國九十八年六月.