臺灣博碩士論文加值系統

本論文包含兩個主題：3倍VDD之雙向混合電壓共容輸入輸出緩衝器，以及具有製程及溫度補償之2倍VDD輸出緩衝器。
第一個主題探討一可容許3倍VDD雙向混合電壓共容輸入輸出緩衝器，本設計以堆疊電晶體的方式構成一可共容至3倍額定電壓之輸出級，再藉由一動態閘極偏壓產生電路及一浮動N井電路產生適當電壓準位，提供輸出級電晶體在傳送或接收訊號時所需之偏壓。而接收高於額定電壓之訊號時，利用N型電晶體之箝制技術將電壓箝制至低電壓，以避免輸入級電晶體閘極氧化層過度應力的問題。本設計以TSMC 0.18 μm CMOS製程實現，並可接收或傳送0.9 V至5.0 V之訊號。
第二個主題提出一具有製程及溫度補償之2倍VDD輸出緩衝器。本設計提出一新型製程及溫度變異之偵測電路，可分別偵測N型電晶體與P型電晶體所屬的角落，並且在驅動電流較低的製程角落補償輸出級電晶體之驅動電流；反之在驅動電流較強的角落則降低其驅動電流，使輸出訊號之電壓迴轉率（slew rate）在不同的環境下，仍維持在一定的範圍內。

This thesis is composed of two parts : a 3×VDD bidirectional mixed-voltage-tolerant I/O buffer, and a 2×VDD output buffer with process and temperature compensation.
In the first topic, a 3×VDD bidirectional mixed-voltage-tolerant I/O buffer, which is able to tolerate 3×VDD using stacking transistors in the output stage, is proposed. These transistors are biased by corresponding voltage levels which are generated by a dynamic gate bias generator and a floating N-well circuit when transmitting or receiving signals. In order to prevent the input stage transistors
from gate-oxide overstress, an NMOS clamping technique is used to block high input voltages. This design can receive and transmit 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5.0 V) signals, which has been implemented using TSMC 1P6M 0.18 μm CMOS process.
The second topic shows a 2×VDD output buffer with process and temperature compensation using 1P6M 0.18 μm CMOS process. In this design, a novel process and temperature variation detector is proposed to detect the corners of NMOS and PMOS, respectively. The driving capability of the output stage is enhanced at those corners with low output currents. By contrast, the driving currents is reduced at those corners with high output currents to reduce the variation of output slew rate.

目錄
致謝 ......................................................................................................... v
摘要 ........................................................................................................ vi
Abstract ................................................................................................ vii
目錄 ......................................................................................................viii
圖目錄 .................................................................................................... xi
表目錄 ................................................................................................... xv
第一章 概論 ......................................................................................... 1
1.1 研究動機 ..................................................................................... 1
1.2 相關技術與文獻探討 ................................................................. 4
1.2.1 傳統輸入輸出單元 ............................................................... 4
1.2.2 傳統混合電壓共容輸出入單元 ............................................ 5
1.2.3 全混合電壓共容輸出入單元................................................ 7
1.2.4 製程、電壓及溫度變異偵測電路 ........................................ 8
1.3 論文大綱 ................................................................................... 10
第二章 3倍VDD之雙向混合電壓共容輸入輸出緩衝器 ............... 11
2.1 簡介 ........................................................................................... 11
2.2 電路架構與設計 ....................................................................... 11
2.3 電路設計 ................................................................................... 13
2.3.1 輸出級電路(output stage) ................................................... 13
2.3.2 前置驅動電路（Pre-driver） ............................................. 14
2.3.3 動態閘極電壓產生電路（Dynamic gate bias generator） . 15
2.3.4 浮動N井電路（Floating N-well circuit） ......................... 26
2.3.5 輸入級電路（Input Stage circuit） .................................... 27
2.4 電路模擬與預計規格 ............................................................... 29
2.4.1 電路模擬結果 ..................................................................... 29
2.4.2 預計規格 ............................................................................. 34
2.5 晶片佈局 ................................................................................... 34
2.6 晶片實作與量測結果 ............................................................... 35
2.6.1 靜電放電防護能力量測 ..................................................... 42
2.6.2 量測結果討論 ..................................................................... 43
第三章 具有製程及溫度補償之2倍VDD輸出緩衝器 .................. 44
3.1 簡介 ........................................................................................... 44
3.2 電路架構與設計 ....................................................................... 45
3.3 電路工作原理 ........................................................................... 47
3.3.1 2倍VDD輸出緩衝器（2×VDD output buffer） .............. 47
3.3.2 時脈產生器(Clock generator) ............................................. 53
3.3.3 NMOS門檻電壓偵測電路 ................................................. 54
3.3.4 PMOS門檻電壓偵測電路.................................................. 56
3.3.5 比較器................................................................................. 57
3.3.6 NMOS邏輯電路與PMOS邏輯電路 ................................ 58
3.4 電路模擬與預計規格 ............................................................... 60
3.4.1 電路佈局後模擬結果 ......................................................... 60
3.4.2 預計規格列表 ..................................................................... 64
3.5 晶片佈局 ................................................................................... 65
3.6 結果與討論 ............................................................................... 66
第四章 研究結果與結論 .................................................................... 68
參考文獻 ............................................................................................... 69

[1] www.itrs.net
[2] S.-K. Shin, W. Yu, Y.-H. Jun, J.-W. Kim, B.-S. Kong, and C.-G. Lee, “Slew-rate-controlled output driver having constant transition time over process, voltage, temperature, and output load variations,” IEEE Trans. Circuits and Systems-II Express Briefs, vol. 54, no. 7, pp. 601-605, Jul. 2007.
[3] S.-K. Shin, W. Yu, Y.-H. Jun, J.-W. Kim, B.-S. Kong, and C.-G. Lee, “A slew rate controlled output driver using PLL as compensation circuit,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1227-1233, Jul. 2003.
[4] K. Leung, “Controlled slew rate output buffer,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 5.5/1-5.5/4, May 1988.
[5] S.-W. Choi and H.-J. Park, “A PVT-insensitive CMOS output driver with constant slew rate,” in Proc. IEEE Asia-Pacific Conf. on Advanced System Integrated Circuits, pp. 116-119, Aug. 2004.
[6] J. Williams, “Mixing 3V and 5V Ics,” IEEE Spectrum, vol. 30, no. 3, pp. 40-42, Mar. 1993.
[7] T. Furukawa, D. Turner, S. Mittl, M. Maloney, R. Serafin, W. Clark, J. Bialas, L. Longenbach, and J. Howard, “Accelerated gate-oxide breakdown in mixed-voltage I/O circuits,” in Proc. Of IEEE Int. Reliability Physics Symp., pp. 169-173, Apr. 1997.
[8] E. Takeda and N. Suzuki, “An empirical model for device degradation due to hot-carrier injection,” IEEE Electron Device Letter, vol. 4, no. 4, pp. 111-113, Apr. 1983.
[9] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors,” IEEE Trans. Circuit and Systems I: Regular Papers, vol. 53, no. 9, pp. 1934-1945, Sep. 2006.
[10] M. J. M. Pelgrom, and E. C. Dijkmans, “A 3/5 V compatible I/O buffer,” IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 823-825,
70
Jul. 1995.
[11] M.-D Ker, and C.-S Tsai, “Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic n-well bias circuit,” in Proc. Of IEEE Int. Symp. Circuits and Systems, vol. 5, pp. V-97-V-100, May 2003.
[12] C.-H. Chung and M.-D Ker, “Design on mixed-voltage-tolerant I/O interface with novel tracking circuit in a 0.13-μm CMOS technology,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, pp. 577-580, May 2004.
[13] M.-D. Ker and S.-L. Chen, “Design of mixed-voltage I/O buffer by using NMOS-blocking technique,” IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2324–2333, Oct. 2006.
[14] T.-J. Lee, T.-Y. Chang, and C.-C. Wang, “Mixed-voltage-tolerant I/O buffer design,” in Proc. Int. Symp. On Integrated Circuits, pp. 596-599, Sept. 2007.
[15] T.-J. Lee, W.-C. Chang, and C.-C. Wang, “Mixed-voltage-tolerant I/O buffer using a clamping dynamic gate bias generator,”in Proc. 2007 IEEE Region 10 Conf. – Tencon, pp. 1-4, Nov. 2007.
[16] C.-H. Lim and W.-R. Daasch, “Output buffer with self-adjusting slew rate and on-chip compensation,” in Proc. IEEE Symp. On IC/Package Design Integration, pp. 51-55, Feb. 1998.
[17] J.-B. Lee, K.-H. Kim, C. Yoo, S. Lee, O.-G. Na, C.-Y. Lee, H.-Y. Song, J.-S. Lee, Z.-H. Lee, K.-W. Yeom, H.-J. Chung, I.-W. Seo, M.-S. Chae, Y.-H. Choi, and S.-I. Cho, “Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin ×16 DDR SDRAM,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 68-69, 431, Feb. 2001.
[18] C. Hua, D. Stout, and J. Chickanosky, “Process, voltage and temperature compensation of off-chip-driver circuits for sub-0.25-μm CMOS technology,” in Proc. IEEE Int. ASIC Conference and Exhibit, pp. 279-282, Sep. 1997.
[19] Y.-H. Kwak, I. Jung, H.-D. Lee, Y.-J. Choi, Y. Kumar, and C. Kim, “A one cycle lock time slew-rate-controlled output driver,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 408-611, Feb. 2007.
71
[20] Q.-A. Khan, G.-K. Siddhartha, D. Tripathi, S.-K. Wadhwa, and K. Misri, “Techniques for on-chip process voltage and temperature detection and compensation,” in Proc. Int. Conf. on VLSI Design, Jan. 2006.
[21] H. Sanchez, J. Siegel, C. Nicoletta, J. P. Nissen, and J. Alvarez, “A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-um, 3.5-nm Tox, 1.8-V CMOS technology,” IEEE J. Solid-State Circuits, vol. 34, no. 11, pp. 1501-1511, Nov. 1999.
[22] S.-L. Chen and M.-D. Ker, “An output buffer for 3.3-V applications in a 0.13-μm 1/2.5-V CMOS process,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, no. 1, pp. 14-18, Jan. 2007.
[23] M.-D. Ker, T.-M. Wang, and F.-L. Hu, “Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process,” in Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, pp. 1047-1050, Aug. 2008.
[24] T.-J. Lee, Y.-C. Liu, and C.-C. Wang, “1.8 V to 5.0 V mixed–voltage- tolerant I/O buffer with 54.59% output duty cycle,” in Proc. Of IEEE Int. Symp. On VLSI Design, Automation and Test, pp. 93-96, Apr. 2008.
[25] www.ics.ee.nctu.edu.tw/~mdker/ESD/index.html
[26] C.-C. Wang, J.-W. Liu, and R.-C. Kuo, “A 0.9 V to 5 V mixed-voltage I/O buffer using NMOS clamping technique,” in Proc. IEEE Int. Conf. IC Design and Technology, pp. 29-32, May 2009.
[27] C.-C. Wang, R.-C. Kuo, and J.-W. Liu, “0.9 V to 5 V bidirectional mixed-voltage I/O buffer with an ESD protection output stage,” IEEE Trans. Circuits and Systems-II: Express Briefs, (accepted, paper no. TCAS-II 7263, Apr. 2010)