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研究生:黃文祺
研究生(外文):Wen-chi Huang
論文名稱:應用於壓電感應器並使用數位方法增強輸出範圍的讀出電路
論文名稱(外文):A Readout Circuit for Piezoelectric Sensors with Digital Range-Enhancement
指導教授:勞伯特律格
指導教授(外文):Robert Rieger
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:93
中文關鍵詞:壓力記錄訊號還原壓電感應器動態範圍讀出電路
外文關鍵詞:realignmentpressure recordingpiezoelectric sensorsread-outdynamic range
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本論文提出一種可以完全積體化的前端讀出電路並可用於記錄來自壓電感應器的輸出訊號。此電路利用定期重置輸入訊號以避免輸入電壓超過緩衝電路的輸入範圍。由於經過緩衝放大器之後的數位訊號可以在數位域中移除重置訊號造成的影響,因此可以忠實表現出輸入力量大小的變動。而不同的訊號還原演算法也在這篇論文被探討,相關的模擬與量測的結果也證明了此系統的動態範圍可達 52.5 dB 並且可記錄到 0.55 Hz 的頻率,而且也可以有效減少輸入漏電流對系統的影響。此系統是以 Cadence 的 Spectre, Synopsys 的 HSPICE 等電路模擬軟體與 National Instruments 的 LabVIEW 做模擬驗證等工作,而不同的還原演算法則是利用 MATLAB 模擬比較還原後的波形。此讀出電路利用台灣積體電路製造股份有限公司所提供的 0.35 μm 2-poly 4-metal CMOS 製程技術完成下線。最後,本論文記錄了實際系統測量與模擬器模擬的結果比較。此讀出電路在電壓為 3V 時功率消耗為 230μW 而壓力記錄範圍為 0.4N 到 169N 。
This thesis presents a fully integratable read-out front-end for recording from piezoelectric sensors. It is proposed to periodically reset the input signal to avoid build-up of large voltages across the circuit input terminals. Digitizing the signal after buffering allows removal of the reset steps in the digital domain, thus yielding a faithful representation of the applied input force variation. Different realignment algorithms are presented in this thesis, and the measured results as well as the simulated results from a bench setup are reported which confirm a 52.5 dB dynamic range and recording of frequencies as low as 0.55 Hz. It is also shown the effect of input current leakage is reduced. The proposed system is simulated using the Cadence Spectre simulator, Synopsys HSPICE and National Instruments LabVIEW to confirm its operation. Different realignment algorithms are examined using MATLAB. The read-out circuit is further realized by 0.35 μm 2-poly 4-metal Taiwan Semiconductor Manufacturing Company (TSMC) process technology. The chip measured results are reported and compared to the simulation. The measured implementation yields a pressure recording range of 0.4 N to 169 N, while consuming 230 μW from 3 V supplies.
Acknowledgments i
摘要 iii
Abstract v
Contents vii
List of Figures ix
List of Tables xv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Piezoelectric Sensor 5
Chapter 2 Pressure Measurement System 9
2.1 System Structure 9
2.2 Prototype Circuit 13
2.3 Integrated Circuit Design 14
2.3.1 Switch Circuit 14
2.3.2 Integrated Front-end Buffer 16
2.3.3 Chip Layout 23
2.4 Realignment Algorithm 24
2.4.1 Realignment Approach 1: Constant Second Derivative 25
2.4.2 Realignment Approach 2: Constant Slope 28
2.4.3 Realignment Approach 3: Constant Amplitude 30
2.4.4 Realignment Approach 4: Digital Low-Pass Filter 32
2.5 FPGA Implementation 33
2.5.1 CLKGEN 35
2.5.2 PIEZO and ADC 35
2.5.3 ADC_CS 35
2.5.4 READ_ADC_DO 36
2.5.5 NEW_RESET_PIEZO 37
2.5.6 SHIFT_REG 37
2.5.7 COUNT_RESET_TIME 38
2.5.8 COMPUTE 38
2.5.9 OUTPUT_STAGE 42
2.6 Display 43
Chapter 3 Measurement 45
3.1 Testing Environment 45
3.2 Measurement Results 47
3.2.1 Piezoelectric Sensor 47
3.2.2 Switch Circuit and Front-End Buffer 49
3.2.3 Complete System 49
3.3 Specification Comparison 54
Chapter 4 Conclusion and Future Work 55
4.1 Conclusion 55
4.2 Future Work 55
References 57
Appendix A1
Appendix A Matlab Code for Realignment Algorithm A1
Appendix B Verilog Code for FPGA Implementation A3
Appendix C LabVIEW Program A13
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