臺灣博碩士論文加值系統

本篇論文提出一個適用於 IEEE 802.16e 標準多重碼率低密度同位元檢查碼 (Low-Density Parity-Check code，LDPC) 解碼器，其主要修正舊有在不同碼率下重疊化架構，如此可以提升硬體利用率與具彈性的參數化設計。LDPC 解碼主要藉由位元節點 (Variable node) 運算和檢查節點 (Check node) 運算重複遞迴所完成。我們利用Beneš 網路來完成位元節點和檢查節點間的繞線，但由於不同碼率的解碼器所對應的位元節點和檢查節點間的繞線也不同，如使用多個Beneš 網路會造成硬體複雜度的提升，因此我們提出重疊化架構來減少全平行下Beneš 網路的複雜度以提升硬體使用率。

In this thesis, a multi-rate LDPC (Low-Density Parity-Check code) decoder circuit is proposed for IEEE 802.16e standard. In the proposed circuit, we modify the overlapping structure for different code rate of the LDPC decoder to enhance the hardware utilization ratio and provide flexible parametric design. LDPC decoding is completed by the recursive operations between variable nodes and check nodes. We use Beneš network to implement the wire-routing of the operations between variable nodes and check nodes. However, the decoders with different code rates may result in different Beneš networks and increase the hardware complexity. We propose a modified overlapping structure to reduce the complexity of parallelized Beneš network and to increase the hardware utilization ratio.

誌謝 i
摘要 ii
Abstract iii
目錄 iv
圖索引 vi
表索引 viii
第一章 簡介 9
1.1 研究動機 9
1.2 論文簡介 10
1.3 論文架構 10
第二章 低密度同位元檢查碼 11
2.1 低密度同位元檢查碼 11
2.1.1 通訊系統基本架構 11
2.1.2 線性區塊碼 (Linear block code) 12
2.1.3 LDPC 及Tanner 圖 13
2.1.4 LDPC編碼在IEEE 802.16e 標準的資訊 14
2.2 編碼方法 17
2.2.1　IEEE 802.16e標準編碼方法 17
2.2.2 編碼流程圖 18
2.3 LDPC解碼 19
2.3.1 Sum-product 演算法 (SPA) 20
2.3.2 LLR sum-product 演算法 (LLR-SPA) 21
2.3.3 Minimum-sum演算法 (MSA) 23
2.4 Matlab模擬驗證 24
2.4.1 LDPC在不同碼率下的效能 25
2.4.2 LDPC在不同循環次數作解碼 25
2.5 量化 26
第三章 硬體實現 28
3.1 平行化與序列化架構 28
3.2 時間重疊 28
3.3 Muti-rate硬體實現 32
3.3.1 Beneš network 架構 33
3.3.2 控制訊號 34
3.4 本設計之架構 36
3.4.1 檢查節點程序電路單元架構 36
3.4.2 位元節點程序電路單元架構 38
第四章 系統模擬與晶片設計 38
4.1 Modelsim 模擬 38
4.2 Synthesis結果 40
第五章 結論 42
參考文獻 43

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