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研究生:王泰盛
研究生(外文):Tai-sheng Wang
論文名稱:40奈米晶圓製程覆晶無鉛凸塊封裝材料與結構組合研究
論文名稱(外文):Lead Free Bump Assembly Material and Structure Study for 40 nm Wafer Technology
指導教授:楊台發
指導教授(外文):Young,Tai-Fa
學位類別:碩士
校院名稱:國立中山大學
系所名稱:機械與機電工程學系研究所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:69
中文關鍵詞:無鉛覆晶封裝可靠性測試40奈米晶圓技術底膠
外文關鍵詞:UnderfillLead Free Bump40nm Wafer TechnologyReliability Test
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目前覆晶封裝方法大多是利用有機基板配合錫鉛凸塊作為封裝之電性連接點,藉此減少了電流所需的距離,其中作為連接的凸塊亦因環保考量將傳統的錫鉛凸塊改良成無含鉛之材料,而晶圓之製程也由55奈米進階至40奈米,因晶圓介電材料作了改變導致後續覆晶封裝所需要的材料也需作進一步的改變以配合晶圓的製程改變,介電層材質之改變,導致原先的晶圓切割需導入雷射切割而不再使用傳統之刀片切割,而考慮到介電層線路材質本身易脆的特性,需於保護層另鋪設一層Polyimide作為緩衝區,預防低介電層線路的崩裂。
在覆晶組裝流程過程中,晶片結合與迴焊製程,助焊劑之清洗與底膠製程及植球製程,需考慮晶片與迴焊過程中迴焊的降溫的速度,將可以降低無鉛凸塊的熱應力;同時研究不同的UBM結構,對於凸塊與低介電層電路的強度關係,可預測凸塊破裂的破壞模式。而底膠之選擇可確實保護凸塊與低介電層之線路,但產品的翹曲與製程管控必須良好(本論文選擇了四種不同的底膠作分析研究)。並透過信賴性測試找出最適合的材料,包含凸塊的合金組成,UBM結構, 底膠的選擇,製程參數的管控使其信賴性達到最佳化。
研究結果顯示,使用雷射預切割晶圓,可避免40nm 晶圓於信賴性測試時LowK層之崩裂。在UBM結構上,透過覆晶產品已不點底膠以做溫度循環測試,來分析UBM 結構,結果顯示使用POU架構的UBM較RPI結構更為完善,並且不易造成LowK 崩裂。且分析使用凸塊印刷製程的Sn99.7wt%Cu0.7wt%(SnCu0.7)凸塊與C4 Sn96.5wt%Ag3.0wt%Cu0.5wt%(SAC305)合金所撘配的凸塊聯接結構式可為最佳的構造。
使用不同底膠種類與基板做為封裝,發現不同CTE的基板Core並不易造成產品之翹曲現象,而底膠本身Tg特性的差異,對於產品之翹曲具最大的影響因素。而不同的底膠對於PI接合性強弱有差異,本研究發現底膠UA9具最佳性,可以承受信賴性測試高達TCB1000之溫度循環測試。製程之最佳材料配合低成本無鉛銲錫凸塊的UBM結構合金併運用製程參數管控可有效應用於工業生產。
Solder bump is used to connect organic substrate with chip to form Flip Chip package. Comparing to wire bond package, the path is reduced so the electrical performance is much better. Due to the environmental concern, eutectic bump is replaced by lead-free bump gradually. Meanwhile, since wafer technology is improved from 55 nm to 40 nm, the material for dielectric layers is also changed so the material for the package need to revised to meet the characteristic of wafer. Now the laser grooving is adopted before blade sawing to accommodate the brittleness of new 40nm wafer. Also, one extra polyimide is added in the wafer fabrication to reinforce the robustness of the circuit.
The stress inside the lead-free bump can be reduced by optimizing the temperature of the reflow process and the speed of cooling. Different UBM structure is also reviewed to find out its affect on the strength of bump and low-K circuit so the failure mode of bump can be predicted. The selection of underfill need to be well considered so, the warpage of package can be reduced, the maximum protection of bump and low-K circuit can be achieved, and the process is easier to control. (The four underfills are reviewed) The reliability test is utilized to decide the best bump composition, the structure of UBM, the selection of underfills and the process parameter.
By adding the laser grooving in the wafer sawing process, the chance of crack on die low-K layer is reduced during the reliability test. As for the UBM structure, the POU is better than RPI to reduce the crack of die low-K layer. The result is verified on the package with no underfill by Temperature cycle. Last, the matching of SnCu0.7 bump with SAC305 C4 pad has the best result.
During the research, the variance of CTE for the core of substrate contributes less warpage of package, comparing to the difference of Tg for underfills. The adhesion of underfills varies and the underfill UA9 has the best result. The flip chip package with underfill UA9 can passes TCB1000.
The optimization of UBM structure for lead-free bump is researched and discussed. Composition of the lead-free bump, process parameter, and cost, those factors are also studied.
論文審定書 ........................................................................................................ I
ACKNOWLEDGEMENT .................................................................................. II
CONTENTS .................................................................................................... III
FIGURE INDEX ............................................................................................. IV
TABLE INDEX ............................................................................................... VI
摘要 ............................................................................................................... VII
ABSTRACT ................................................................................................. VIII
ABBREVIATION ............................................................................................ IX
1. INTRODUCTION ......................................................................................... 1
1.1 FLIP CHIP INTRODUCTION .......................................................................... 1
1.2. FLIP CHIP PROCESS FLOW INTRODUCTION ................................................ 3
1.3 40 NM WAFER TECHNOLOGY ...................................................................... 5
1.4 RESEARCH DESIGN ................................................................................... 7
2. BASIC PRINCIPLE ...................................................................................... 9
2.1 FLIP CHIP DIE ATTACHMENT ...................................................................... 9
2.2 UNDERFILL MECHANICAL PROPERTIES ..................................................... 10
2.3 BUMP SOLDER/C4 PAD ALLOY REQUIREMENT .......................................... 13
2.4 FLIP CHIP RELIABILITY MECHANISM ......................................................... 16
3. EXPERIMENT I (MATERIAL AND STRUCTURE STUDY) ....................... 18
3.1 SOLDER BUMP AND SUBSTRATE C4 ALLOY MATERIAL SELECTION ............ 18
3.1.1 Solder Bump and Substrate C4 Alloy Material Selection Result ....... 19
3.1.2 Solder Bump and Substrate C4 Alloy Result and Discussion . 23
3.2 RPI AND POU BUMP STRUCTURE SIMULATION ......................................... 24
3.3 UBM STRUCTURE FOR POU AND RPI RESULT AND DISCUSSION ................ 31
4. EXPERIMENT II (PACKAGE LEVEL STUDY) .......................................... 35
4.1 DOE DESIGN .......................................................................................... 35
4.2 ASSEMBLY PROCESS MONITOR RESULT ................................................... 38
4.3 RELIABILITY RESULT ............................................................................... 44
4.4 RESULTS AND DISCUSSION ...................................................................... 55
5. CONCLUSIONS ........................................................................................ 57
6. REFERENCE ............................................................................................. 59
1.Http://www.tsmc.com/chinese/b_technology/b01_platform/b0101_ adva
2.http://www.tsmc.com.tw, “40 and 45 Nanometer Process Technology”
3.Edited by Sanka Ganesan, Michael Pecht, “ Lead-Free Electronics”, 2004 Edition, Calce, Maryland, p47-63, p164-165
4.http://www.sgte.org/
5.JESD22-A104,”Temperature Cycling” rev D, March 2009, [JEDEC]
6.Hance,W. B., and N.-C. Lee,”Voiding Mechanisms in SMT,” China Lake’s 17thAnnual Electronics Manufacturing Seminar, China Lake, CA, February 2–4, 1993.
7.Ning-Cheng Lee, “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP and Flip Chip Technologies”, Newnes, New York 2000, p171-180
8.AMD, U.S. Patent 11/832,486
9.Data sheet from Hitachi Chemical Corp.
10.Data sheet from Sumitomo Chemical Corp.
11.Data sheet from Namics Corp
12.Ahn, Eun-Chul et al., “Reliability of Flip Chip BGA Package on Organic Substrate,” Proc 50th Electronic Components and Technology Conference, May 2000, pp. 1215 – 1220. [conference]
13.Qing Tan et al., “Failure Mechanisms of flip chip DCA assembly using eutectic Solder “, 2000 IEEE, [conference]
14.J-STD-030, “Guideline for Selection and Application of Underfill Material for Flip Chip and other Micropackages”, Draft 7, Dec 2000, pp. 9-10. [JEDEC]
15.Vijay Wakhharkar et al., “Material Technologies for Thermomechanical Management of Organic Package”, Intel Technology Journal Vol. 9, issue 4, 2005
16.Ken Gilleo, “Area Array Packaging Processes: for BGA, Flip Chip, and CSP”, McGraw-Hill , October 2003, p135-139
17.John H. Lau “Flip Chip Technologies” ,McGraw-Hill, Inc New York, NY , 1995
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