臺灣博碩士論文加值系統

本篇論文提出一個適用於 IEEE 802.16e 系統的低密度奇偶校驗證碼（Low-Density Parity-Check code，LDPC）解碼器電路。此模組可支援19種區塊長度，包含區塊長度576，672，….，2304 等位元數。本篇論文提出了新的重疊化LDPC解碼器設計，修正舊有的重疊化架構，讓元件利用率達到100%效果。LDPC解碼主要藉由位元節點（Variable node）運算和檢查節點（Check node）運算重複遞迴所完成。然而此解碼器在尚未優化下位元節點和檢查節點利用率僅有50%，我們可以利用重疊化設計來提高利用率。在IEEE 802.16e 1/2碼率下，一般的重疊化設計至多僅能提高至75%[2]，而我們所提出的重疊化設計能將位元節點和檢查節點利用率達到100%。在相同工作頻率下可提高25%吞吐量。在比較器上，利用快速且小面積的方法來完成[1]。加法器上，我們使用進位保留法（CSA）[8]來取代一般的樹狀加法器。
在使用CMOS 0.18μm 1P6M 製程的情況下，此LDPC解碼器其晶片面積為3.11 x 3.08 mm2，經過模擬驗證輸出的資料速率至少可達到78.4 MHz，可以符合IEEE 802.16e系統之規格需求。

A circuit design of Low Density Parity Check (LDPC) decoder for IEEE 802.16e systems is with new overlapped method is proposed in this thesis. This circuit can be operated with 19 modes which are corresponding to block sizes of 576, …, 2304. LDPC decoders can be implemented by using iterations with Variable Node and Check Node Processes. The hardware utilization ratio, which can be enhanced from 50% to 100% by using our proposed overlapped method, is better than traditional overlapped method. In [2], the traditional overlapped method utilization ratio just can be enhanced from 50% to 75% for IEEE 802.16e LDPC decoder with code rate 1/2. Under the same operating frequency, our proposed method can further increase 25% when compared with traditional overlapped method [2]. In this thesis, we also propose two circuit architectures to increase the operating frequency. First, we use a faster comparison circuit in our comparison unit [1]. Second, we use Carry Save Adder（CSA）method [8] to replace the common adder unit.
The circuit is carried out by TSMC CMOS 0.18μm 1P6M process with chip area 3.11 x 3.08 mm2. In the gate level simulation, the output data rate of this circuit is above 78.4MHz, so the circuit can meet the requirement of IEEE 802.16e system.

誌謝 i
摘要 iii
Abstract iv
目錄 v
圖索引 vii
表索引 ix
第一章　簡介與研究動機 1
第二章　低密度奇偶效驗證碼之編碼與解碼 2
2.1　低密度奇偶效驗證碼基本原理 2
2.1.1　通訊系統基本架構 2
2.1.2　LDPC碼基本原理 3
2.1.3　LDPC編碼在IEEE 802.16e 標準的資訊 5
2.2　編碼方法 7
2.2.1　IEEE 802.16e標準編碼方法 7
2.2.2　編碼流程圖 8
2.3　解碼方式 9
2.3.1　Sum of Product 演算法 (SPA) 11
2.3.2　Minimum-Sum algorithm (MSA) 15
2.4　matlab模擬驗證流程圖 16
2.5　LDPC在不同遞迴次數作解碼 18
2.6　量化 23
第三章　硬體架構 25
3.1　平行化與序列化架構 25
3.2　時間重疊 25
3.3　提出新的時間重疊概念 27
3.4　提出的設計架構 29
3.3.1　檢查節點程序電路單元架構 32
3.3.1　位元節點程序電路單元架構 34
第四章　系統模擬與晶片設計 38
4.1　Modelsim 模擬 38
4.2　佈局與繞線 41
4.3　DRC驗證 42
4.4　LVS驗證 43
4.5　晶片量測 45
4.5.1　量測步驟與流程 45
4.5.1　預計規格與實測結果 45
第五章　結論 49
參考文獻 52

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