臺灣博碩士論文加值系統

本論文研究主要是提出十二位元每秒二百萬次取樣率電流導向式數位/類比轉換器(Current-Steering DAC)。該轉換器利用5+7區段式電流導向式數位/類比轉換器架構方式設計。
本研究採用區段式電流導向式數位/類比轉換器之架構設計，其中5位元的高位元(MSB)為等電流源(Unary Current Cell)，並配合溫度器解碼(Thermometer Code)等電流源的方式來降低差動非線性誤差(Differential Nonlinearity Error)及縮小面積。另外7位元(LSB)部份採用加權二進制電流源(Binary-Weighted Current Cell)。為了使12位元數位輸入訊號的同步與降低突波能量，透過數位門閂(Digital Latch)電路來改善，而在差動開關(Differential Switch)的切換順序，則採用二維距心式之電流源開關切換順序；並為了增加輸出阻抗及提高SFDR，在高、低位元之電流源設計方面，皆採用疊接電流源(Cascode Current Cell)方式設計。
為了達到每秒二百萬次取樣率及1mm2面積設計規格，本研究利用蒙地卡羅
及台積電0.18微米製程設計錦囊，透過不匹配模型(Mismatch-Model)與蒙地卡羅分析法進行設計，再根據Jose Bastos等人所提出最小面積乘積(WL)min，在設計的過程中透過此方法可使設計的電路在電晶體的尺寸縮小有很大的改善，並能夠在良率的提升上有相當大的改善，除此之外設計者能在未做佈局前就能得知，目前所設計的電路是否能滿足在製程變異(Process-Variation)的情況下仍能正常的運作，這對整個晶片的設計流程(Design-Flow)有相當大的助益。
蒙地卡羅模擬結果，以輸入訊號為100MHz且取樣率為200MHz的情況下， DNL及INL分別為0.6LSB及0.8LSB、晶片面積為0.2mm2。該晶片採用TSMC 0.18um 1P6M CMOS 製程來實現。

We propose a 12-Bit 200MS/S Current-Steering DAC based on a Segmented (5+7) current-steering architecture. In order to decrease the differential nonlinearity error (DNL) and reduce area, we employ Unary-Current cell with thermometer code decoder for the 5MSBs and Binary-Weighted Current Cell for the 7LSBs. In order to synchronize inputs and improve glitch energy, we use a digital latch approach. Differential switch order is very critical for DNL, so we use the Two Dimensional Centroid method. In order to enhance DAC output impedance and SFDR, both the MSB and LSB are implemented with Cascode Current Cell.
To meet the 200MS/S and 1mm2 area spec, we perform Monte-Carlo Analysis with TSMC 0.18um Process Design Kit (PDK) and Mismatch Model. Because the Mismatch Model includes Process-Variation information, it can achieve more simulation accuracy than the corner model.
Monte-Carlo simulation result, shows that when the input signal is 100MHz and sample rate is 200MHz, we have DNL=0.6LSB , and INL =0.8LSB. The chip area is 0.2mm2 in a TSMC 0.18um 1P6M CMOS Process.

摘 要 I
誌 謝 III
目 錄 IV
表目錄 VI
圖目錄 VII
第一章 緒論 1
1.1 研究動機 1
1.2 論文貢獻 2
1.3 名詞解釋 4
1.4 電流源設計流程圖 5
1.5 場效應電晶體與台積電0.18微米製程設計錦囊不匹配模型 6
1.5.1利用台積電蒙地卡羅模型計算最小通道面積乘積(WL)min 6
1.5.2高速度/解析電流導向式數位/類比轉換器設計趨勢 7
1.5.3十二位元二百萬次取樣率電流導向式數位/類比轉換器設計規格 10
1.6 論文組織 11
第二章 數位類比轉換器基本架構 12
2.1 理想數位類比轉換器 12
2.2 靜態參數、動態參數、傳輸參數 13
2.2.1解析度 13
2.2.2偏移誤差 13
2.2.3增益誤差 14
2.2.4累積非線性誤差 14
2.2.5差動非線性誤差 15
2.2.6穩定時間 15
2.2.7訊雜比 15
2.2.8訊號雜訊失真比 16
2.2.9無雜散動態範圍 16
2.2.10有效位元數 16
2.3 數位類比轉換器基本架構 17
2.3.1電流導向式 17
2.3.2溫度計解碼型式 18
2.3.3區段型式 19
2.3.4基本解碼式 20
2.3.5加權二進制式 21
2.4 電流導向式數位/類比轉換器佈局配置 22
第三章 電流導向式數位類比轉換器電路設計 25
3.1 十二位元電流導向式數位/類比轉換器系統架構圖 25
3.2 區段化電流導向式數位/類比轉換器設計 26
3.2.1電流源單元 27
3.3 五位元等電流源 28
3.4 七位元加權二進制電流源 40
3.5 數位門閂電路 42
3.5.1高臨限電壓門閂電路 42
3.5.2低電荷貫穿高臨限電壓門閂電路 44
第四章 晶片佈局模擬結果 46
4.1 十二位元電流導向式數位/類比轉換器的佈局配置 46
4.1.1全晶片佈局 46
4.2 雙矩式切換組合 47
4.2.1等電流源與門閂電路佈局配置 48
4.2.2等電流源與門閂電路佈局 49
4.3 七位元加權二進制電流源與門閂電路佈局 50
4.3.1七位元加權二進制電流源與門閂電路佈局 50
4.4 數位門閂電路佈局與模擬結果 51
4.5 十二位元電流導向式數位/類比轉換器DNL與INL模擬結果 52
4.5.1估計等電流源隨機誤差 52
4.5.2十二位元電流導向式數位/類比轉換器 52
4.6 數位/類比轉換器佈局模擬結果 66
4.6.1利用Calibre中LPE工具，萃取電路雜散電阻與電容電路 66
4.6.2方塊電阻與相互連接的電容表格 67
4.6.3具有雜散電阻、電容效應之電流源單元電路 67
4.6.4萃取電路雜散電阻與電容結果 68
4.6.5十二位元電流導向式數位/類比轉換器佈局後模擬結果 69
4.7 數位/類比轉換器近期發表比較結果 71
第五章 研究結論及未來工作展望 72
參考文獻 73

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