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研究生:顏景陽
研究生(外文):Yen, Ching-Yang
論文名稱:提出3D-IC與系統封裝設計之快速模擬軟體的新架構
論文名稱(外文):Proposing A New Fast 3D Electromagnetic-based RLC Extraction Software Platform for 3D-IC and System-in-Package Designs
指導教授:張克正
指導教授(外文):Chang, Keh-Jeng
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:98
語文別:中文
論文頁數:146
中文關鍵詞:電路模擬傳輸線系統封裝設計兩層印刷電路板四層印刷電路板分散式模型
外文關鍵詞:Circuit simulationInterconnectSystem-in-Package Designs2-layer PCB4-layer PCBdistributed model
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隨著產品所需的執行頻率來到數十億赫茲階層,電阻、電容、電感等寄生參數對三維晶片(3D-IC)及系統級封裝(System in Package, SiP)的影響也越來越大。過去我們應用在封裝、印刷電路板、超大型積體電路設計或無線電頻上的設計方法學大多是採用夾心帶線(stripline)或是微帶線(microstrip)等結構,對三維晶片及系統級封裝的設計的幫助有限。有鑑於此,為解決三維晶片與系統封裝設計上傳輸線問題,我們提出一套快速模擬三維晶片與系統封裝設計上傳輸線的軟體新架構。

過去,因為產品所需的執行頻率較低,所以SiP中用來連接系統內各個元件的金屬線可以被視為完美的聯接線,不會有延遲及干擾的產生。隨著頻率越來越高,我們必須將系統級封裝中的金屬聯接線視為傳輸線(Transmission line)。

因此,傳輸線所衍生出關於訊號完整度(signal integrity)的種種問題,例如:延遲(RC delay)、基底耦合(substrate coupling)、串音(crosstalk)、阻抗匹配(impedance match)、電磁干擾(Electromagnetic Interference, EMI)、信號反彈(reflection)等問題都需要在設計流程中更精確模擬計算,並且去了解、量化這些傳輸線所衍生出訊號完整度問題。

本篇論文將會利用三維的電磁模擬軟體,對三維晶片及系統級封裝進行電感、電容與電阻的分析,設計出一套快速抽取電阻、電容、電感值的軟體架構並觀察各種寄生效應對電路的影響,進而量化三維晶片及系統級封裝上的種種訊號完整度問題。

我們將提出一個整合性高、速度快、能夠輕易的學習使用的電性模型軟體,來協助使用者,希望藉此提高產品良率,降低設計迴圈,並且更能準確模擬並維持信號完整度及電源供應完整度的問題,以求對三維晶片及系統級封裝產業上有更大的貢獻。
The trend of advanced 3D IC and system-in-package (SiP) designs is toward gigahertz-level operating frequencies and very compact form factors. Leveraging the design methodologies of packaging, PCB board, VLSI, or RF, is not practical during advanced 3D IC or SiP designs because those methodologies assume the availability of microstrips and striplines, which are rarely available to the designers of 3D IC or SiP. Therefore, interconnect problems on 3D-IC and system-in-package mandate a new design software platform that can address the needs of high-performance 3D IC and SiP designers.
In the low frequency design, metal connections between different components can be thought as perfect connections which will not affect the performance. However, the requirement for high frequency product has become a trend now. Those connections used in the package should be modeled as transmission line.
Therefore, those issues of signal integrity such as RC delay, IR drop, substrate coupling, crosstalk, impedance match, Electromagnetic Interference, reflection … etc on 3D IC and system-in-package need to be modeled accurately and be taken into account in the design flow so that simulation and modeling of these interconnections have become more and more important. It is important to quantify these values and need more researches for better understanding them.
We’ll use 3 dimensional field solvers to analyze the basic electrical properties of 3D IC and system-in-package in this thesis. Then we’ll design a fast 3D electromagnetic-based RLC Extraction Software Structure and observe the real behavior of the circuit, and we quantified the signal integrity problems on 3D IC and system-in-package.
We’ll provide an accurate and user-friendly simulation software advanced interconnect modeling software (AIMS) to help designers to increase the design productivity, to minimize the design cycle, and to maintain the signal integrity and power integrity in this thesis. We can give suggestions to the designers on how to achieve better signal integrity in high-speed 3D-IC and SiP system-in-package.
目錄

英文摘要……………………………………………………………………………1
中文摘要……………………………………………………………………………2
目錄…………………………………………………………………………………3
圖片目錄……………………………………………………………………………6
表格目錄……………………………………………………………………………14

第一章 簡介 14
1.1 前言………………………………………………………………………14
1.2 系統單晶片與系統級封裝………………………………………………17
1.3 Flip chips、Wirebonds與Through hole vias………………………………28
1.4 Very few夾心帶線與微帶線………………………………………………22
1.5 四層印刷電路板、兩層印刷電路板與一層印刷電路板………………23
1.6 高頻與分散式模型………………………………………………………24
1.7 動機與提供的程式………………………………………………………25

第二章 背景介紹和相關研究 26
2.1 印刷電路板………………………………………………………………26
2.2 電阻、電容、電感………………………………………………………27
2.3 分散式模型………………………………………………………………29
2.4 信號完整度………………………………………………………………30
2.5 串音………………………………………………………………………30
2.6 Raphael及Fasthenry………………………………………………………30
2.7 阻抗匹配…………………………………………………………………31
2.8 Perl/Tk……………………………………………………………………32
2.9 抽取電阻、電容、電感值的方法………………………………………33
2.9.1 我們抽取電容值的方法與文獻上的經驗公式比較 ……………34
2.9.2 我們抽取電阻、電感值的方法與文獻上的經驗公式比較………35








第三章 兩層印刷電路板模擬實驗 38
3.1 兩層印刷電路板基礎實驗………………………………………………38
3.1.1 金屬連線長度對電阻、電容、電感的影響……………………38
3.1.2 金屬連線寬度對電阻、電容、電感的影響……………………40
3.1.3 金屬連線線距對電阻、電容、電感的影響……………………42
3.1.4 金屬連線頻率對電阻及電感的影響……………………………44
3.2 兩層印刷電路板延伸實驗………………………………………………46
3.2.1 兩層印刷電路板線路間的角度分析…………………………46
3.2.2 Bottom layer金屬角度對電阻、電容、電感的影響…………48
3.2.3 上下層金屬結構間角度與覆蓋面積對電感的影響分析……79
3.2.4 上下層金屬結構間角度與覆蓋面積對電容的影響分析……81
3.2.5 上下層金屬結構間角度與覆蓋面積對電阻的影響分析……83
3.2.6 上下層金屬結構間角度與覆蓋面積對電性的影響分析……85
3.3 兩層印刷電路板的結構分析……………………………………………86
3.4 兩層印刷電路板的模擬切斷方法………………………………………90
3.5 兩層印刷電路板的模擬方法小結………………………………………92

第四章 兩層板與四層板的比較 93
4.1 兩層板上下層距與四層傳輸層至Gnd層距離相同時…………………93
4.1.1 不同頻率線寬及線長下四層板與兩層板的電感比較………94
4.1.2 不同頻率線寬及線長下四層板與兩層板的電阻比較………97
4.1.3 不同線寬及線長下四層板與兩層板的電容比較……………99
4.1.4 不同頻率線寬及線長下四層板與兩層板的阻抗比較………100
4.2 兩層板上下層距與四層板上下傳輸層間距離相同時…………………103
4.2.1 不同頻率線寬及線長下四層板與兩層板的電感比較…………104
4.2.2 不同頻率線寬及線長下四層板與兩層板的電阻比較…………107
4.2.3 不同線寬及線長下四層板與兩層板的電容比較………………110
4.2.4 不同頻率線寬及線長下四層板與兩層板的阻比較……………111










第五章 更完整的SiP傳輸線結構 113
5.1 兩層板與四層板上的Through Hole Via…………………………………114
5.1.1 D1(Via寬度)對電性的影響………………………………………116
5.1.2 D2-D1 (Via邊緣到周邊結構距離)對電性的影響………………117
5.1.3 S1(VIA與VIA間距離)對電性的影響…………………………118
5.1.4 H(Via高度)對電性的影響………………………………………119
5.1.5 F(Via頻率)對電性的影響………………………………………120
5.2 Wirebond…………………………………………………………………121
5.2.1 Wirebond長度對電阻、電容、電感的影響……………………121
5.2.2 Wirebond寬度對電阻、電容、電感的影響……………………123
5.2.3 Wirebond頻率對電阻及電感的影響……………………………125

第六章 EDA程式架構 127

第七章 NTHU對3D-IC與SIP上傳輸線的整理與未來工作 130

參考文獻…………………………………………………………………………132

附錄 134
附錄1. Raphael input file for 2-layer PCB…………………………………134
附錄2. Fasthenry input file for 2-layer PCB………………………………137
附錄3. Raphael input file for 4-layer VIA…………………………………140
附錄4. Fasthenry input file for 4-layer VIA………………………………143
參考文獻

[1] C.-C. Tang, “Using 3D Electromagnetic Simulation Software to Improve Design for Manufacturability for High-Speed 2-Layer PCB,” Master Thesis, NTHU, 2008.

[2] S.-C. Chou, “A Fast 3D RLC Extraction and SPICE Auto-gen Software for 3D Interconnect Designs,” Master Thesis, NTHU, 2008.

[3] T.-M. Wu, “3D Interconnect Capacitance Modeling for Off-Chip High Performance Designs,” Master Thesis, 2008.

[4] K.-J. Chang, et al., “Three-dimensional electromagnetic modeling of system in package and system-on-glass transmission-line parameters for DFM,” 2008.

[5] K.-J. Chang, et al., “HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs,” Hewlett-Packard Company, Palo Alto, CA 94304, USA, 1991.

[6] C. Huang, “A New Verification Strategy to Rigorously Test Two Pieces of Electromagnetic Field Simulation Software,” Master Thesis, NTHU, 2007.

[7] W. Fei, “Comprehensive Evaluations of Three-Dimensional Electromagnetic Field Simulation Software for Accurate Nanometer Device Modeling,” Master Thesis, NTHU, 2007.

[8] L.-F. Chang, et al., “In-depth Speed and Accuracy Comparison of Inductance Extraction for SoC Signal Integrity and Tool Integration,” 2002.

[9] T. Liu, “Accurate Nanometer Inductance Modeling for SoC Designs,” Master Thesis, NTHU, 2005.

[10] W.Chuang, “Accurate inductance modeling of various wirebonds for high-performance system-in-package designs,” Master Thesis, NTHU, 2005.

[11] RAPHAEL User’s Manual, Version 2003.09, 2003.

[12] FastHenry USER’s GUIDE, Version 3.0 11, 1996.

[13] K. S. Oh, et al., “Capacitance Computations in a Multi-layered Dielectric Medium Using the Closed-form Spatial Green’s Functions,” IEEE Trans, 1994.

[14] W. Delbare and D. D. Zutter, “Space-domain Green’s Function Approach to the Capacitance Calculation of Multi-conductor Lines in Multi-layered Dielectrics With Improved Surface Charge Modeling,” IEEE Trans, 1989.

[15] M. J. Tsuk and J. A. Kong, “A Hybrid Method for the Calculation of the Resistance and Inductance of Transmission Lines with Arbitrary Cross Sections,” IEEE Trans, 1991.

[16] M.-J. Huang, “Using 3D field solvers to enhance signal integrity in Sip,” Master Thesis, NTHU, 2008.
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