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研究生:李建旻
研究生(外文):Lee, Chien-Min
論文名稱:FastandAccurateProcessorPowerSimulationbyPre-CharacterizationandAnnotation
論文名稱(外文):藉由預先描繪及註釋以達到快速且準確的處理器功耗模擬
指導教授:蔡仁松
指導教授(外文):Tsay, Ren-Song
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:98
語文別:英文
論文頁數:38
中文關鍵詞:功耗模擬系統層級
外文關鍵詞:power simulationsystem level
相關次數:
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這篇論文提出了一個新穎的功耗模擬技巧,透過預先的描繪與註釋來達到快速又準確的處理器功耗模擬。 追求低功耗已經成為系統晶片設計必要的條件,所以快速且準確的功耗估算對於系統設計來說是相當重要的。然而,由於模擬的模組與功耗模組間相互約束的關係,造成現行的系統層級的處理器功耗估算技巧必須在估算準確度與模擬速度上做取捨。相對的,我們所提出的新穎技巧,在準確度上,採用靜態功耗分析(預先描繪與註釋),在速度上,則是採取動態功耗計算(執行時模擬)。從實驗結果發現,採用本篇論文所提出的方法可同時達到快速且準確的功耗模擬,速度上可超過每秒兩億個指令,準確度與閘極層級的功耗模擬器相比誤差在百分之三以內。
This paper proposes a novel power simulation technique utilizing pre-characterization and annotation to achieve fast and accurate processor power simulation. Since low power consumption has become a default requirement for system-on-chip (SOC) designs, fast and accurate power estimation is essential for system designs. However, constrained by tight coupled simulation and power models, current system-level processor power estimation techniques have to compromise estimation accuracy for simulation speed. In contrast, our proposed novel technique performs static power analysis (pre-characterization and annotation) for accuracy and then dynamic power calculation (runtime simulation) for speed. The experimental results show that the proposed approach can achieve both high efficiency (more than 200 MIPS) and high accuracy, within 3 % error rate compared with gate-level power simulation.
1. Introduction
2. Related Work
3. A Novel Processor Power Simulation Approach
3.1. Power Characterization
3.1.1. Intra-Basic Block Power Characterization
3.1.2. Inter-Basic Block Power Correction
3.1.3. Cache Miss Penalty Power Correction
3.2. Power Annotation Algorithm
3.3. Simulation
3.4. Discussions
4. Experiment
5. Conclusion and Future Work
[1] L. Lavagno, et al., Electronic Design Automation For Integrated Circuits Handbook, CRC Press, Inc. Boca Raton, FL, USA, 2006.
[2] V. Tiwari, et al., “Instruction Level Power Analysis and Optimization of Software”, in Journals of VLSI Signal Processing Systems, 1996, pp. 223-233.
[3] CACTI 5.3, http://quid.hpl.hp.com:9081/cacti/
[4] D. Brook, et al., “Wattch: a Framework for Architectural-Level Power Analysis and Optimizations”, in Proceedings of ISCA, 2000, pp. 83-94.
[5] E. Cheung, et al., “Fast and Accurate Performance Simulation of Embedded Software for MPSoC”, in Proceedings of ASPDAC, 2009, pp. 552-557.
[6] R. –B. Atitallah, et al. “An MPSoC Performance Estimation Framework Using Transaction Level Modeling”, in Proceedings of RTCSA, 2007, pp. 525-533.
[7] Synopsys Design Compiler, PrimePower, http://www.synopsys.com
[8] M. C.-T. Lee, et al., “Power Analysis and Minimization Techniques for Embedded DSP Software”, in Transactions of VLSI Systems, 1997, pp. 123-135.
[9] M. Sami, et al., “Instruction-Level Power Estimation for Embedded VLIW Cores”, in Proceedings of CODES, 2000, pp. 34-38.
[10] A. Varma, et al., “Accurate and Fast System-Level Power Modeling: An XScale-Based Case Study”, in Transactions of Embedded Computing Systems (TECS), vol. 7, issue 3, 2008.
[11] W. Ye, et al., “The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool”, in Proceedings of DAC, 2000, pp. 340-345.
[12] G. Contreras, et al., “The XTREM Power and Performance Simulator for the Intel XScale Core: Design and Experiences”, in Transactions of Embedded Computing Systems (TECS), vol. 6, issue 1, 2007.
[13] Y. –H. Park, et al., “Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow”, in Proceedings of CODES+ISSS, 2008, pp. 255-260.
[14] T. Givargis, et al., “Trace-Driven System-Level Power Evaluation of System-On-a-Chip Peripheral Cores”, in Proceedings of ASP-DAC, 2001, pp. 306-312.
[15] L. Gao, et al., “Multiprocessor Performance Estimation Using Hybrid Simulation”, in Proceedings of DAC, 2008, pp. 325-330.
[16] OR1200 OpenRISC Processor, http://www.opencores.org
[17] J. Zhu, et al., "A Retargetable, Ultra-Fast Instruction Set Simulator," in Proceedings of DATE, 1999, pp. 62-69.
[18] T. D. Givargis, et al., “Instruction-Based System-Level Power Evaluation of System-on-a-Chip Peripheral Cores”, in Proceedings of ISSS, 2000, pp. 163-169.
[19] Yi-Len Lo, et al., “Cycle Count Accurate Memory Modeling in System Level Design”, in Proceeding of CODES+ISSS, 2009, pp. 287-294
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