|
[1] Texas Instruments, “OmapTM4 mobile applications platform,” 2009. [2] Qualcomm, “The snapdragon platform,” 2010. [Online]. Available: http://www.qctconnect.com/products/snapdragon.html [3] T. Lin, C. Liu, S. Tseng, Y. Chu, and A.Wu, “Overview of ITRI PAC project–from VLIW DSP processor to multicore computing platform,”in Proc. IEEE Int. Symp. VLSI Des., Automation, and Test, 2008, pp.188–191. [4] J. Nickolls, I. Buck, M. Garland, and K. Skadron, “Scalable parallel programming with cuda,” Queue, vol. 6, no. 2, pp. 40–53, 2008. [5] I. Buck, T. Foley, D. Horn, J. Sugerman, K. Fatahalian, M. Houston, and P. Hanrahan, “Brook for gpus: stream computing on graphics hardware,”in SIGGRAPH ’04: ACM SIGGRAPH 2004 Papers. NewYork, NY, USA: ACM, 2004, pp. 777–786. [6] A. Munshi, “Opencl: Parallel computing on the gpu and cpu.” SIGGRAPH,2008. [7] A. D. Reid, K. Flautner, E. G. Evans, and Y. Lin, “Soc- c: efficient programming abstractions for heterogeneous multicore systems on chip,”in CASES ’08: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems. NewYork, NY, USA: ACM, 2008, pp. 95–104. [8] W. Thies, M. Karczmarek, and S. Amarasinghe, “Streamit: A language for streaming applications,” in Compiler Construction, ser. Lecture Notes in Computer Science, R. N. Horspool, Ed. Berlin, Heidelberg: Springer Berlin Heidelberg, March 2002, vol. 2304, ch. 14, pp.49–84. [9] K. Fatahalian, D. R. Horn, T. J. Knight, L. Leem, M. Houston, J. Y. Park, M. Erez, M. Ren, A. Aiken, W. J. Dally, and P. Hanrahan, “Sequoia: programming the memory hierarchy,” in SC ’06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing. New York, NY, USA: ACM, 2006, p. 83. [10] K.-Y. Hsieh, Y.-C. Liu, P.-W. Wu, S.-W. Chang, and J. K. Lee, “Enabling streaming remoting on embedded dual- core processors,” in Parallel Processing, 2008. ICPP ’08. 37th International Conference on, Sept. 2008, pp. 35–42. [11] T. Mattson, B. Sanders, and B. Massingill, Patterns for parallel programming. Addison-Wesley Professional, 2004. [12] C. A. Moritz, M. Frank, M. M. Frank, W. Lee, and S. Amarasinghe, “Hot pages: Software caching for raw microprocessors,” 1999. [13] D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/software Interface. Morgan Kaufmann, 2005. [14] P. F. Felzenszwalb and D. P. Huttenlocher, “Efficient belief propagation for early vision,” Computer Vision and Pattern Recognition, IEEE Computer Society Conference on, vol. 1, pp. 261–268, 2004. [15] J. Sun, N. Zheng, and H. Shum, “Stereo matching using belief propagation,”IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 25, no. 7, pp. 787–800, 2003. [16] C.-W. Huang, W.-K. Shih, Y. Hsu, and J.-K. Lee, “Configurable sidbased multi-core simulators for embedded system education,”in Workshop on Embedded Systems Education’09, Grenoble, France, 2009. [17] D. C.-W. Chang, “PAC digital signal processor,” in Proceedings of Fall Microprocessor Forum, 2006. [18] K. Hsieh, Y. Lin, C. Huang, and J. Lee, “Enhancing microkernel performance on vliw dsp processors via multiset context switch,” Journal of Signal Processing Systems, vol. 51, no. 3, pp. 257–268, 2008. [19] Y.-C. Lin, C.-L. Tang, C.-J. Wu, M.-Y. Hung, Y.-P. You, Y.-C. Moo, S.-Y. Chen, and J. K. Lee, “Compiler supports and optimizations for PAC VLIW DSP processors,” in Proceedings of the 18th International Workshop on Languages and Compilers for Parallel Computing, 2005.
|