Soft error becomes an important reliability issue in advanced technologies. Previous works which tolerate soft error induce significant timing penalty because of additional delay elements and C elements are needed. The goal of this paper is to design a high-performance soft-error tolerant structure. Since soft error occurs infrequently, our idea is to design an efficient soft-error detection architecture and to rely on the flush mechanism of CPU to do the error correction. If this is not a CPU design, we can also keep an error free signal by a particular circuitry and recover by restoring the error free signal. We propose two different soft-error-tolerant structures to accommodate different design styles. Our experimental results show that the proposed soft-error-tolerant structure achieves significant improvement in timing and power penalty.

在先進的製程中，“軟錯誤”已經成為一個影響晶片可靠度的重要議題。舊有容錯方法在晶片上加入delay buffer和C-element，所以會造成不可忽略的效能負擔。此篇論文的目的即在設計一個高效能的軟錯誤容忍機制。因為軟錯誤發生的頻率很低，我們主要的概念是設計一個有效的軟錯誤偵測機制，然後依賴那些原本就存在於晶片中的回覆機制去做錯誤更正，例如CPU中的flush機制。如果晶片不是CPU的設計的話，我們也可以採用另一種方式去維持一個不易出錯的值，如果發生錯誤，就可以籍由將這個不易出錯的值重新讀取到記憶體元件中來更正錯誤。我們提出二種不同的軟錯誤容易機制，他們分別適用在特定的晶片上。實驗結果顯示，我們提出的架構在效能和功率消耗上，達到很大的改善。

Abstract i
List of Contents: ii
List of Figures: iii
List of Tables: iv
Chapter 1 Introduction 1
Chapter 2 Related Work 6
Chapter 3 Soft-Error Tolerant Design 10
3.1 LSD Flip-flop 14
3.2 HLSD Flip-flop 17
3.3 LSD-R Flip-flop 20
3.4 HLSD-R Flip-flop 24
Chapter 4 Cell Design, Characterization and Analysis 29
4.1 Cell Design And Characterization 29
4.2 Cell-Level Analysis 31
Chapter 5 Optimization Framework 34
Chapter 6 Experiment Results 36
6.1 Five-Stage TinyRISC Design 36
6.2 Soft-Error-Tolerant Strategies 38
6.3 Result Analysis 42
Chapter 7 Conclusion 44
Reference 45

[1] N. D. P. Avirneni, V. Subramanian, and A. K. Somani, "Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Systems," in Proc. Intl. Conf. on Dependable Systems and Networks(DSN), pp. 185-194, 2009.
[2] D. Binder, E.C. Smith, and A.B. Holman, “Satellite Anomalies from Galactic Cosmic Rays,” IEEE Trans. on Nuclear Science, vol. 22, pp. 2675-2680, Dec. 1975.
[3] A. M. Finn, “The System Effect of Single Event Upsets”, Proc. 7th Computers in Aerospace Conf., Monterey, pp. 994-1002, Oct. 1989.
[4] D. F. Heidel et al., “Alpha-particle Induced Upsedts in Advanced CMOS circuits and Technology,” IBM Journal of Research and Dev., May 2008, vol. 52, no. 3,, pp. 225-232
[5] C. Hunges and J. H. Patel, “Latch Design for Transient Pulse Tolerance,” in Proc. Intl. Conf. on International Conference on Computer Design(ICCD), pp. 385-388, 1994.
[6] J. Joshi, R. R. Rao, D. Blaauw and D. Sylvester, “Logic SER Reduction Through Flipflop Redesign,” in Proc. Intl. Symp. on Quality Electronic Design(ISQED), pp. 611-616, 2006.
[7] T. Karnik, P. Hazucha, and J. Patel., “Characterization of Soft Errors Caused by Single Event Upsets in CMOS Process”, IEEE Trans. on Dependable and Secure Computing, vol.1, pp.128-143, April 2004
[8] S. Krishnaswamy, I. L. Markov, and J. P. Hayes, “On the Role of Timing Masking in Reliable Logic Circuit Design”, Proc. of DAC, pp. 924-929, 2008
[9] R. E. Lyons, W. Vanderkulk, “The use of triple-modular redundancy to improve computer reliability”, IBM Journal of Research and Development , Volume:6, Issue:2, pp200-209, April 1962
[10] A. Mahmood, E. J. McCluskey, “Concurrent error detection using wachdog processors-a survey”, IEEE Transactions on Computers, Volume:37, Issue:2, pp. 160-174, Feb. 1988
[11] D. G. Mavis and P. H. Eaton, “Soft Error Rate Mitigation Techniques for Modern Microcircuits”, Proc. Int. Reliability Physics Symp., Dallas, TX, 2002, pp. 216-225
[12] T. C. May and M.H. Woods, “A New Physical Mechanism for Soft Errors in Dynamic Memories,” Proc. IEEE 16th Ann. Int’l Reliability Physics Symp., pp. 33-402, Apr. 1978.
[13] N. Miskov-Zivanov, D. Marculescu, “MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits”, Proc. of DAC, pp. 767-772, 2008
[14] N. Miskov-Zivanov, D. Marculescu, ”Modeling and Optimization for Soft-Error Reliability of Sequential Circuits,” IEEE TCAD, 2008, vol 27. no.5 pp. 803-816.
[15] S. Mitra, M. Zhang, S. Waqas, N. Seifert, B. Gill, and K. S. Kim, “Combinational Logic Soft Error Correction”, Proc. IEEE Int. Test Conf., 2006, Paper No. 29.2
[16] P. Mongkolkachit, B. Bhuva, “Design Technique for Mitigation of Alpha Particle-Induced Single-Event Transients in Combinational Logic”, IEEE Trans. on Device and Materials Reliability, Volume:3, Issue: 3, Sept. 2003 Pages:89-92
[17] B. Narasimham et al. “Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies,” IEEE Trans. on Nuclear Science , 54(6):2506-2511, Dec. 2007.
[18] M. Nicolaidis, “Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies,” Proc. of VLSI Test Symposium, pp. 86-94, 1999
[19] J. H. Patel and L. Y. Fung. ”Concurrent Error Detection in ALU’s by Recomputing with Shifted Operands”. in IEEE Trans. on Computers, Vol.C-31:589–595, Jul 1982.
[20] R. R. Rao, K. Chopra, D. Blaauw, D. Sylvester, “An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits, ”, in Proc. Intl. Conf. on Design Automation and Test in Europe(DATE), pp. 1-6, March 2006.
[21] T. Sakata, T. Hirotsu, H. Yamada and T. Kataoka, “A Cost-effective Dependable Microcontroller Architecture with Instruction-level Rollback for Soft Error Recovery,” in Proc. Intl. Conf. on Dependable Systems and Networks(DSN), pp. 256-265, 2007.
[22] W. Sheng, L. Xiao and Z. Mao, “Soft Error Optimization of Standard Cell Circuits Based on Gate Sizing and Multi-objective Genetic Algorithm,” in Proc. of DAC, pp. 502-507, 2009
[23] P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvisi, “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” Proc. Intl. Conf. on Dependable Systems and Networks(DSN), pp. 389-398, 2002
[24] F. Wang and V. D. Agrawal, “Single event upset: An embedded tutorial,” in VLSI Design, held jointly with 7th Interantional Conference on Embedded Systems., 2008, pp.429-434
[25] N. J. Wang and S. J. Patel, “ReStore: Symptom-based Soft Error Detection in Microprocessors,” in IEEE Trans. on Dependable and Secure Computing, vol. 3, pp. 188-201, Jul.-Sep. 2006.
[26] B. Zhang, W. Wang, and M. Orshansky. FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. In Proc. of International Symposium on Quality Electronic Design (ISQED), March 2006.
[27] M. Zhang and N. R. Shanbhag. A Soft Error rate Analysis (SERA) Methodology. In Proc. of ACM/IEEE International Conference on Computer Aided Design (ICCAD), pp. 111-118, 2004.
[28] Q. Zhou and K. Mohanram. Gate sizing to Radiation Harden Combinational Logic. In IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 1, pp. 155-166, January 2006.
[29] “Gate Arrays Wane While Standard Cells Soar: ASIC Market Evolution Continues,” Technical report, Semico Research Corporation, Nov. 20002. Business Wire