臺灣博碩士論文加值系統

在現今的系統晶片中，為了支援更多的功能特性，匯流排整合了許多系統元件諸如處理器、加速器、以及其他周邊控制器。 然而，隨著整合複雜度的增加，確保一個正確無誤的系統晶片是越來越困難。 為了達到診斷以及除錯的需要，追蹤匯流排上的傳輸可以觀察到整體系統執行的情況。

在此論文中，我們針對AHB提出了一個應用於系統晶片之可程式化即時匯流排追蹤器。 為了使得設計者更容易分析匯流排上的訊號，我們設計了一個Transaction Generation Unit將匯流排上的訊號轉換成Transaction 的形式。 並且提供了一個可規劃的事件觸發單元去捕捉使用者想觀察到的存取行為。 在追蹤的過程中，我們以一個Trace Window來觀察匯流排上的訊號。 一個Trace Window 能讓我們觀察到事件觸發前後的匯流排行為。 為了減少追蹤時所產生的資料量，我們針對不同類型的追蹤資料設計不同的壓縮方法，並且針對單筆傳輸以及突發傳輸採取不同的壓縮機制。 對於單筆傳輸以及突發傳輸，可以分別達到91% 以及97%的壓縮率。 此壓縮結果讓我們得以在合理的追蹤腳位數目下將追蹤資料即時的傳送出來。 為了不影響追蹤時整體系統的效能，我們透過JTAG介面來存取匯流排追蹤器。

在分析過程中，我們以國立清華大學以及國立交通大學共同開發的Starfish系統來當作我們的測試環境。 在TSMC 0.13μm的製程之下，匯流排追蹤器花費了48.8 K gates並可以支援200MHz的速度。 我們將匯流排追蹤器整合到Starfish系統，追蹤器可以透過16根腳位即時的追蹤資料，並只佔了整體7.2%的面積。 最後，我們列舉了死結、突發傳輸錯誤等例子來展示追蹤器除錯以及診斷的能力，並且透過追蹤器我們實際發現到Starfish系統中DMA介面傳輸的錯誤。

In modern SoC, the on-chip bus infrastructure integrates many dedicated components such as processors, accelerators, and other dedicated peripherals for the demand of more functionality. With the increasing complexity, the guarantee of a bug-free system is more difficult. For the need of diagnosing and debugging, tracing the operations on the bus provides a great observability to the system execution.

In this thesis, we propose a real-time configurable bus tracer which targets at the AHB bus infrastructure. For facilitating observability, a Transaction Generation Unit which provides a method of modeling the bus signals to a transaction is proposed. We support a configurable event trigger to capture the transactions which the designer is interested. In addition, a trace mechanism of configurable Trace Window is introduced which is able to explore transactions before and after trigger event whenever the trigger occurs. For reducing huge amount of the trace data, a transaction is classified to 4 types of trace data which are compressed with different methods. Besides, we also provide a compression mechanism for both single mode and burst mode, and the 91% and 97% compression ratio can be achieved respectively. As a result, the bus tracer is capable of transporting the trace data through a constrained on-chip trace port. To be non-intrusive to the system, the bus tracer is programmed through the JTAG interface.

As a case study, the bus tracer is integrated to the Starfish system which is developed by National Tsing-Hua University and National Chiao-Tung University. The bus tracer runs at 200MHz and costs about 48.8K gates in TSMC 0.13μm technology. In overall system, the area overhead of the bus tracer is about 7.2% with a 16-bit trace port. For demonstrating the capability of debugging and diagnosing, there are examples of detecting deadlock, multicycle waiting, and burst transfer violation with our bus tracer. In real design, we find a protocol bug of DMA interface through tracing bus operations in the Starfish system.

1 Introduction 1
1.1 Introduction of SoC Debugging and Tracing . . . . . . . . . . . . . . . . . . 1
1.2 The Challenge of Bus Debugging and Tracing . . . . . . . . . . . . . . . . . 3
1.3 Motivation and Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Previous Work 6
2.1 AHB Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Prior Trace and Debug Suppport Implementation . . . . . . . . . . . . . . . 7
2.3 Starfish Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Components of Bus Tracer and Implementation 12
3.1 Overview of the Bus Tracer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Transaction Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 Transaction Generation FSM . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Compression Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1 Address Compression Method . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2 Control Compression Method . . . . . . . . . . . . . . . . . . . . . . 22
3.3.3 Data Compression Method . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.4 State Compression Method . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 Packeting Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1 Header Definition and Packet Format . . . . . . . . . . . . . . . . . . 29
3.4.2 Packet Format of Each Trace Type . . . . . . . . . . . . . . . . . . . 30
3.5 Trace Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.1 Configurable Event Trigger . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.2 Trace Window Concept . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.3 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.6 Multi-Stage Trace Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.6.1 Compression and Packeting Stages . . . . . . . . . . . . . . . . . . . 43
3.6.2 Aligning and Multi-Port FIFO Stages . . . . . . . . . . . . . . . . . . 45
4 Analysis of Compression Method and Hardware Cost 47
4.1 Benchmarks and Behavioral Model for Compression Analysis . . . . . . . . . 47
4.2 Comparison between the Signal Level Trace and the Transaction Level Trace 50
4.2.1 Introduction to the Signal Level Trace . . . . . . . . . . . . . . . . . 50
4.2.2 The Benefit of the Transaction Level Trace . . . . . . . . . . . . . . . 52
4.3 Analysis of the Compression Method . . . . . . . . . . . . . . . . . . . . . . 54
4.3.1 Address Compression Analysis . . . . . . . . . . . . . . . . . . . . . . 54
4.3.1.1 Multi-Source Differential Compression . . . . . . . . . . . . 55
4.3.1.2 The Compression Ratio on Different Transfer Mode . . . . . 56
4.3.2 Control Compression Analysis . . . . . . . . . . . . . . . . . . . . . . 56
4.3.2.1 Dictionary Compression . . . . . . . . . . . . . . . . . . . . 57
4.3.2.2 The Compression Ratio on Different Transfer Mode . . . . . 57
4.3.3 Data Compression Analysis . . . . . . . . . . . . . . . . . . . . . . . 57
4.3.3.1 XOR Compression . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.3.2 The Compression Ratio on Different Transfer Mode . . . . . 61
4.3.4 State Compression and Total Compression Ratio . . . . . . . . . . . 62
4.3.4.1 Run-Length Compression . . . . . . . . . . . . . . . . . . . 62
4.3.4.2 Total Compression Ratio . . . . . . . . . . . . . . . . . . . . 64
4.4 Hardware Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.1 The Buffer Size in the Aligning Unit . . . . . . . . . . . . . . . . . . 67
4.4.2 The FIFO Size and the Trace Port . . . . . . . . . . . . . . . . . . . 68
4.4.3 Data and State Compression Modification . . . . . . . . . . . . . . . 69
4.4.3.1 MISR Compression Method . . . . . . . . . . . . . . . . . . 70
4.4.3.2 Modification and Total Compression Ratio . . . . . . . . . . 75
4.4.3.3 Traffic Influence on FIFO Size . . . . . . . . . . . . . . . . . 79
4.4.4 Synthesis Result of Bus Tracer . . . . . . . . . . . . . . . . . . . . . . 82
5 Experiments and Demonstrations 85
6 Conclusion and Future Work 94
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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