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研究生:蔡怡宏
研究生(外文):Tsai, Yi-Hung
論文名稱:相容於邏輯製程之高微縮性非揮發性記憶體研究
論文名稱(外文):Study of Highly-Scalable and Logic-Compatible Non-Volatile Memories
指導教授:金雅琴林崇榮
指導教授(外文):King, Ya-ChinLin, Chrong-Jung
學位類別:博士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:98
語文別:英文
論文頁數:102
中文關鍵詞:非揮發性記憶體金氧半導體邏輯相容
外文關鍵詞:non-volatile memoryCMOSlogic-compatible
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This dissertation proposes several highly2009.11.19 16:32 140.114.23.201 修改
925009 2009.11.19 16:32 140.114.23.201 修改 scalable logic-compatible non-volatile memory cells. High scalability is based on approaches of nitride storage and differential structure. The new nitride-based OTP cell demonstrated in 90nm logic technology allows for two-bit per cell storage. Differential structure extends its data retention time of a floating gate device by doubling sensing window.
A new gateless OTP memory consists of a parasitic ONO structure realized by 90nm and 45nm standard logic CMOS processes. This cell features fast programming, high on/off current window, and full logic process compatibility. Another contact gated OTP memory features the two-bit per cell, in which a compact cell size can be achieved by a virtual ground array.
A differential structure is also proposed and realized with both n-channel and p-channel devices. N-channel differential MTP memory features self-selective programming, which programs the differential floating gates in two steps, thus eliminating complex peripheral circuits and timing. A self-recovery scheme is proposed in the P-channel differential MTP memory, extending the lifetime of this floating gate device by periodical boosting.
In summary, the proposed memory cells are successfully demonstrated in different generations of standard logic CMOS technologies without an additional mask or process modification. The complete compatibility allows these logic non-volatile memory cells to be easily adapted in advanced logic CMOS circuits.
本論文提出並討論數種具高微縮性與邏輯製程相容之非揮發性記憶體架構。所提出的新型logic NVM cells採用寄生之氮化物儲存層及差動式架構達成高相容性及微縮性。氮化物儲存層非揮發性記憶體發展已久,可採用較薄的閘極氧化層,及單胞雙位元的特性。差動式架構則可利用其雙倍的讀取window以提昇浮動閘極的資料保存能力。2009.11.19 16:32 140.114.23.201 修改
925009 2009.11.19 16:32 140.114.23.201 修改
首先,本論文討論一種新型無閘極一次寫入記憶體及其變型。新型無閘極一次寫入記憶體採用寄生於邏輯金氧半製程的ONO結構作為電荷儲存層。其具有快速編程,高讀取window,高整合性的特點。其另外一類型Contact gated記憶體具有單胞雙位元的特性,可以藉由虛擬接地陣列達到極小的單位記憶元面積。
差動式浮動閘極記憶元結構可同時由n型通道及p型通道元件達成。N型通道差動式記憶體具有自我選擇性編程的特色,利用二階段編程可以達成不需增加週邊電路及時序控制的複雜度。P型通道差動式記憶體則具有自我修復能力,利用週期性或啟動時自動boosting來延長浮動閘極式記憶體的資料保存力。
總而言之,這些記憶體完全相容於標準金氧半邏輯製程,且不需額外光罩及製程調整。相容性有助於整合於高階邏輯電路及降低製造成本,提供先進製程中非揮發性記憶體的新解決方案。
Abstract
摘要
Acknowledgement
List of Contents
List of Tables
List of Figures
Chapter 1 Introduction
1.1 Introduction of logic non-volatile memories
1.2 Objectives
1.3 Organization
Chapter 2 Reviews of Highly Scalable Logic Non-Volatile Memories
2.1 Scaling issues involving logic NVM
2.2 Nitride-based logic NVMs
2.2.1 NonOverlapped Implantation (NOI) non-volatile memory
2.2.2 NeoFlash
2.3 Differential structure of logic NVM cell
2.3.1 AEON
2.3.2 PermSRAM
2.4 Summary
Chapter 3 Nitride-Based Gateless One-Time Programmable Memory
3.1 Structure and fabrication
3.2 Operation principles
3.3 Program, erase and read characteristics
3.3.1 Read characteristics
3.3.2 Program Characteristics
3.3.3 Erase characteristics
3.4 Reliability
3.4.1 Disturbances
3.4.2 Endurance
3.4.3 Data retention
3.5 Summary
Chapter 4 Nitride-Based Contact-Gated Two-Bit Per Cell OTP Memory
4.1 Structure and fabrication
4.2 Operation principles
4.3 Characteristics
4.4 Electrical erase characteristics
4.5 Reliability analysis
4.5.1 Disturb & retention characteristics
4.5.2 Charge trapping profile
4.6 Summary
Chapter 5 High Reliability Differential Floating-Gate Memory
5.1 N-channel differential memory
5.1.1 Self-Selective Program (SSP) technique
5.2 P-channel differential memory
5.3 Summary
Chapter 6 Conclusion
Reference
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