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研究生:張書麟
研究生(外文):Chang, Shu-Lin
論文名稱:AHighlyIntegratedWirelessDownlinkInterfaceforCm-rangeContactlessTestingSystems
論文名稱(外文):應用於短距非接觸性測試系統之高整合性無線接收介面設計
指導教授:黃柏鈞黃柏鈞引用關係
指導教授(外文):Huang, Po-Chiun
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:57
中文關鍵詞:無線測試振幅鍵移解調器整合型天線
外文關鍵詞:Wireless testingASK demodulatorOn-chip antenna
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隨著IC晶片複雜度的提升,IC測試的成本也日益增加。為符合一般功能上的需求,一顆傳統的系統晶片包含類比、數位、記憶體甚至射頻前端電路。然而,為因應這些複雜的設計,測試機台也面臨相對於高頻、接腳數量以及取樣時間精細等問題。為克服以上的挑戰,無線測試的方案應運而生。

為實現無線測試,測試機台與待測物皆需要無線通訊模組。此研究即探討了自測試機台的天線端至待測物的無線接收機之電路設計。

為符合測試環境的需要,無線傳輸距離設定在公分等級的規格。藉此,天線部份選擇以電磁近場理論的延伸來設計。基於近場理論的應用,天線於傳送端與接收端都有不同的設計考量。

在高度整合性的考量之下,過於複雜的電路是不符需求的。振幅鍵移解調器提供了相對簡易且低成本的解決方案。此解調電路設計在915MHz的ISM頻帶中,以反向器串接的電路做為一個無電感式的放大器設計,主動式整流器取代了傳統二極體式整流器,為解決傳統架構中常見的訊號失真問題。整流器後方的動態循跡遲滯比較器扮演了類比訊號處理的角色。傳輸的資料速率為每秒500kbits的PWM碼,操作電壓為1.8V,消耗功率則為1.6毫瓦。

在上述的設計下,我們實現了一個低成本的下載端無線通訊介面。由其設計原型與相關的量測數據則驗證了高度整合無線測試系統的可行性。

As much more complicated features implemented in IC (integrated circuits), the cost of IC testing is getting higher. For the general requirement, a typical SOC contains analog, digital, memory or even front-end circuits. However, to satisfy these complicated demands, testing equipment will face to higher frequency, pin count, and timing accuracy issues. To overcome these challenges, a new testing methodology that uses contactless correction is proposed.

To achieve contactless testing, all the testing functions have to be embedded. Moreover, these needs a wireless interface to support the communications between the device under test (DUT) and automatic test equipment (ATE). In this work, we will focus our research on the integrated antenna and the downlink path (ATE to DUT) designs.

Because the communication space is limited within centimeter range, an integrated antenna using near field coupling is adopted. The transmitted antenna size has been carefully evaluated for both signal receiving and adjacent channel interfering.

For downlink receiving, we select 915MHz ISM band to distinguish the channel for uplink. Amplitude Shift Keying (ASK) serves as the modulation scheme for minimal receiver hardware. The receiver comprises a wideband amplifier, a class-C rectifier and a dual-tracking slicer. In addition, a PWM code is embedded into line coding therefore the timing information can be extracted from the wireless channel.

With these techniques we can realized a low cost downlink wireless interface. The whole circuits have been verified in a contactless testing system.

1 Introduction 1
1.1 Overview of Circuits Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Contactless Testing System Proposal 4
2.1 Overview of HOY System . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.2 Hypothesis, Odyssey and Yield . . . . . . . . . . . . . . . . . . . . 5
2.2 HOY System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Testing Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 HOY Development History . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Communication Specification of RF . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Near-field Antenna for HOY 14
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Transmission Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 Derivation and Definition of Electromagnetic Field . . . . . . . . . . 15
3.2.2 Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Consideration in Free Space . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Antenna Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.1 Design Consideration of Transmitted Port . . . . . . . . . . . . . . . 19
3.4.2 Design Consideration of Received Port . . . . . . . . . . . . . . . . 20
3.4.3 Interference Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Implementation and Measurement . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 RF Receiver Architectures 28
4.1 Architecture Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 ASK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.1 Passive RC Envelope Detector . . . . . . . . . . . . . . . . . . . . . 31
4.2.2 Hysteresis Comparator Demodulator . . . . . . . . . . . . . . . . . . 31
4.2.3 Bias-Based Demodulator . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.4 Self-Sampling Demodulator . . . . . . . . . . . . . . . . . . . . . . 33
4.3 Active ASK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.1 String Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.2 Active Envelope Detector . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.3 Dynamic Tracker and Hysteresis Comparator . . . . . . . . . . . . . 37
4.3.4 Buffer and Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4 Design Consideration and Simulation Result . . . . . . . . . . . . . . . . . . 39
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5 Implementation and Measurement Result 44
5.1 Measurement Results of Core Circuits . . . . . . . . . . . . . . . . . . . . . 44
5.1.1 BER Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.2 Jitter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1.3 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2 Measurement Result of Integration System . . . . . . . . . . . . . . . . . . . 47
5.2.1 Measurement Results of Core Circuits with On-chip Antenna . . . . 50
5.2.2 Measurement Results of Core Circuits when Digital Circuits ON . . . 51
5.2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6 Conclusion and FutureWork 55
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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