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研究生:劉家驥
研究生(外文):Liu, Chia-Chi
論文名稱:應用於小電流非揮發性記憶體之抑制飄移偏差電流感測放大器
論文名稱(外文):A Current Mode Sense Amplifier for Small Cell Current Non-Volatile Memory with Offset Suppressing Scheme
指導教授:張孟凡
指導教授(外文):Chang, Meng-Fan
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:93
中文關鍵詞:非揮發性記憶體電流感測放大器抑制飄移偏差
外文關鍵詞:Non-Volatil memoryCurrent sense amplifierOffset free
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  • 被引用被引用:0
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  • 下載下載:40
  • 收藏至我的研究室書目清單書目收藏:0
現今的系統單晶片中,非揮發性記憶體扮演了不可或缺的角色,儲存其他周邊單元之資料並提供重複讀取。隨著製程的進步,單位面積下所能夠放置的記憶體容量也越來越大,但相對的不論是非或閘型快閃記憶體、非及閘型快閃記憶體或是一次性寫入記憶體,其記憶體單元之表示電流也越來越小,產生了讀取困難。此外製程的演進也顯現了電晶體不匹配的現象,而使得小電流的讀取更加困難。
因此,為了能夠仍使用電流讀取的方式來得到高速操作下,我們提出了一個新的電流感測放大器並且具有壓低電晶體不匹配誤差的效果。在所提出的電流感測放大器中,我們對要比較的電流進行採樣放大。其中採樣過程使得比較電流不需經過電晶體臨界電壓的電流電壓轉換而失真。放大部分則利用電流充電之方式來達到放大效果,以避免因電晶體臨界電壓的不同而產生讀取能力不匹配的現象。此外我們也採用了對稱陣列來達到匹配的環境以及平均電流的效果來消除參考電流源的變異度。
最後我們以提出的新電流感測放大器,以九十奈米互補金氧半製程技術建構出一個由五百一十二千字元(512Kb)所組成的一次性寫入記憶體電路。量測顯示以此種電流感測放大器之電路,在供應電壓為一點二伏情況下,以及參考電流源為一百奈安培下,其最小可讀取電流為一百四十奈安培。



In today’s SOC chip, non-volatile memory plays an important role to store the data from other peripheral unit and can read out repeatable. With the technology shrink, the cell array in same area is larger and larger. However, the cell current is also decreased not only NOR type flash but also NAND type flash or OTP and difficult to read. With the nanometer technology, the transistor threshold voltage mismatch gets more pronounced and making the sensing failure easily.
To solve this problem, we propose a new current mode sense amplifier with offset suppress scheme. In this design, we sample the input current and amplify the difference without regard the threshold voltage variation. Furthermore, we use symmetric array to reduce mismatch between cell side and reference side and use average technique to reduce the variation on reference current due to PVT variation.
We apply our design in 90nm CMOS technology within 512Kb OTP. The experiment result shows that, the minimum cell current can be read in 100nA reference current condition and power supply 1.2V is 140nA.

Contents
Page
? Abstract (Chinese)
? Abstract (English)
? Acknowledgements (Chinese)

Chapter 1. Introduction 15
1.1 Applications 15
1.2 Motivation 17
1.3 Contributions 18
1.4 Thesis Overview 18
Chapter 2. Design Challenges of Current Sensing 20
2.1 Array Type 20
2.2 Mismatch 21
2.2.1 Line Edge Roughness (LER) [12, 13] 21
2.2.2 Short Channel Effect [14, 15] 22
2.2.3 Random Dopant Fluctuation (RDF) [17-20] 25
2.3 Sources of Variation Sensitive Parts in Read Path 26
2.3.1 Flash and OTP Cell 27
2.3.2 Current Mirror 28
2.3.3 Sense Amplifier (SA) 31
Chapter 3. Previous Sense Amplifier Circuit (SA) 37
3.1 Fundamentals of Current SA 37
3.1.1 Latch Type SA [28, 29] 37
3.1.2 Mirror Type SA [30-32] 38
3.1.3 Inverter Type SA [33] 39
3.2 Offset Cancellation SA Design 39
3.2.1 Offset Storage [36] 40
3.2.2 Auto-Zeroing Compensate [33, 35, 38] 41
3.2.3 Charge Redistribution Cancellation [39] 42
3.2.4 Threshold Voltage Storage [40] 43
3.2.5 Digital Offset Compensate [41, 42] 44
Chapter 4. Application to Non-Volatile Memory 46
4.1 OTP Cell Characteristic [43] 46
4.2 Read Operation [23, 44] 47
4.3 Macro Implementation 49
4.3.1 Symmetric Array [45] 50
4.3.2 Replica Reference [42] 51
4.3.3 High Voltage Level Shifter [23] 52
4.4 Testchip Design 53
Chapter 5. Proposed Sense Amplifier (SA) 56
5.1 Offset Free Technique 56
5.2 Proposed Scheme Operation 58
5.3 Design Consideration 62
Chapter 6. Analysis and Comparison 71
6.1 Analysis of Proposed SA 71
6.1.1 Function 71
6.1.2 Yield 72
6.1.3 Speed 73
6.1.4 Voltage sensing V.S. Proposed current sensing 75
6.1.5 Limitations 76
6.2 Comparison 79
Chapter 7. Experiments and Conclusion 81
7.1 Experiments Results 81
7.1.1 Test Chip Photo 81
7.1.2 Function Testing 82
7.2 Summary and Conclusion 85
7.3 Future Work 87
References 90


References
[1] C. J. Chevallier, C. H. Siau, S. F. Lim, S. R. Namala, M. Matsuoka, and B. L. Bateman, “A 0.13μm 64Mb Multi-Layered Conductive Metal-Oxide Memory” in ISSCC Dig. Tech. Papers, pp. 260-261, Feb. 2010.
[2] S. K. Lai “Flash memories: Success and challenges” IBM J. Res. & Dev., vol. 52, no. 4/5, pp. 529-535, Jul. Sep 2008
[3] S. Atsumi, A. Umezawa, T. Tanzawa, T. Taura, H. Shiga, Y. Takano, T. Miyaba, M. Matsui, H. Watanabe, K. Isobe, S. Kitamura, S. Yamada, M. Saito, S. Mori, and T. Watanabe, “A Channel-Erasing 1.8-V-Only 32-Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme” IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1648-1654, Nov. 2000.
[4] A. Conte, Gi. Lo Giudice, G. Palumbo, Senior Member, IEEE, and A. Signorello, “A High-Performance Very Low-Voltage Current Sense Amplifier for Nonvolatile Memory” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 507-514, Feb. 2005.
[5] ITRS, “The 2006 International Technology Roadmap for Semiconductors,” 2006 [Online]. Available: http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm
[6] H. Masuda, S. –I. Ohkawa, A. Kurokawa, and M. Aoki, “Challenge: Variability Characterization and Modeling for 650 to 90-nm Processes” IEEE Custom Integrated Circuits Conference, 2005
[7] J. –H. Park, S. –H. Hur, J. –H. Lee, J. –T. Park, J. –S. Sel, J. –W. Kim, S. –B. Song, J. –Y. Lee, J. –H. Lee, S. –J. Son, Y. –S. Kim, M. –C. Park, S. –J. Chai, J. –D. Choi, U- I. Chung, J. –T. Moon, K. –T. Kim, K. Kim and B. –I. Ryu, “8Gb MLC (Multi-Level Cell) NAND Flash Memory using 63nm Process Technology” in IEDM Dig. Tech. Papers, pp. 873-876, Dec. 2004.
[8] D. –C. Kim, W. –C. Shin, J. –D. Lee, J. –H. Shin, J. –H. Lee, S. –H. Hur, I. –G. Baik, Y. –C. Shin, C. –H. Lee, J. –S. Yoon, H. –G. Lee, K. –S. Jo, S. –w. Choi, B. –K. You, J. –H. Choi, D. Park, and K. Kim “A 2Gb NAND Flash Memory with 0.044µm2 Cell Size using 90nm Flash Technology” in IEDM Dig. Tech. Papers, pp. 919-922, Dec. 2002.
[9] J. Lee, S. –S. Lee, O. –S. Kwon, K. –H. Lee, D. –S. Byeon, I. –Y. Kim, K. –H. Lee, Y. –H. Lim, B. –S. Choi, J. –S. Lee, W. –C. Shin, J. –H. Choi, and K. –D. Suh “A 90-nm CMOS 1.8-V 2-Gb NAND Flash Memory for Mass Storage Applications” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1934-1942, Nov. 2003.
[10] M. Ichige, Y. Takeuchi, K. Sugimae, A. Sato, M. Matsui, T. Kamigaichi, H. Kutsukake, Y. Ishibashi, M. Saito, S. Mori, H. Meguro, S. Miyazaki, T. Miwa, S. Takahashi, T. Iguchi, N. Kawai, S. Tamon, N. Arai, H. Kamata, T. Minami, H. Iizuka, M. Higashitani, T. Pham, G. Hemink, M. Momodomi, and R. Shirota “A Novel Self-Aligned Shallow Trench Isolation Cell for 90nm 4Gbit NAND Flash EEPROMs” in Symp.VLSI Circuits Dig. Tech. Papers, pp. 212-213, Jun. 2003
[11] C. –H. Lee, J. Choi, C. Kang, Y.Shin, J. –S. Lee, J. Sel, J. Sim, S. Jeon, B. –I. Choe, D. Bae1, K. Park, and K. Kim “Multi-Level NAND Flash Memory with 63 nm-node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure” in Symp.VLSI Circuits Dig. Tech. Papers, pp. 212-213, Jun. 2006
[12] S. Xiong and J. Bokor, “A Simulation Study of Gate Line Edge Roughness Effects on Doping Profiles of Short-Channel MOSFET Devices” IEEE Trans.on Electron Devices, vol. 51, no. 2, pp. 228-232, Feb. 2004.
[13] Y. Ye, F. Liu, S. Nassif, Y. Cao, “Statistical Modeling and Simulation of Threshold Variation under Dopant Fluctuations and Line-Edge Roughness” IEEE Design Automation Conference, pp. 900-905, 2008
[14] B. Razavi, Design of Analog CMOS Integrated Circuits McGraw-Hill Science, 2001.
[15] B. L. Anderson and R. L. Anderson, Fundamentals of Semiconductor Devices: McGraw-Hill, 2005.
[16] T. –H. Kim, J. Keane, H. Eom, and C.Kim, “Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, pp. 821-829, July 2007.
[17] A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies and S. Saini “Quantum Mechanical Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations and Lowering in Sub 0.1 micron MOSFETs” in IEDM Dig. Tech. Papers, pp. 467-470, Dec. 1999.
[18] D. Reid, C. Millar, G. Roy, R. Sinnott, G. Stewart, G. Stewart and A. Asenov “Prediction of Random Dopant Induced Threshold Voltage Fluctuations in NanoCMOS Transistors” IEEE Int. Simulation of Semiconductor Processes and Devices, pp. 21-24, 2008
[19] T. Mizuno, J.- I. Okamura and A. Toriumi “Experimental Study of Threshold Voltage Fluctuation Due to Statistical Variation of Channel Dopant Number in MOSFET’s” IEEE Trans.on Electron Devices, vol. 41, no. 11, pp. 2216-2221, Dec. 1994.
[20] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland “Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design” IEEE J. Solid-State Circuits, vol. sc-21, no. 6, pp. 1057-1066, Dec. 1986.
[21] A. Balasubramanian, P. R. Fleming, B. L. Bhuva, O. A. Amusan, and L. W. Massengill “Effects of Random Dopant Fluctuations (RDF) on the Single Event Vulnerability of 90 and 65 nm CMOS Technologies” IEEE Trans.on Nuclear Science, vol. 54, no. 6, pp. 2400-2406, Dec. 2007.
[22] A. Asenov, “Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 µm MOSFET’s: A 3-D ‘Atomistic’ Simulation Study” IEEE Trans.on Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998.
[23] G. Campardo, R. Micheloni, and D. Novosel, VLSI-Design of Non-Volatile Memories, Springer, 2005
[24] Riichiro Shirota, Course slides of Flash Memory, NTHU, 2010
[25] P.- C. Huang, Course slides of Analog Integrated Circuits, NTHU, 2008
[26] J. -T. Wu, Course slides of Data Converter Integrated Circuits, NCTU, 2009
[27] J. –T. Wu, and B. A. Wooley “A 100-MHz Pipelined CMOS Comparator ” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1379-1385, Dec. 1988.
[28] T. N. Blalock, and R. C. Jaeger “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 542-548, Apr. 1991.
[29] C. –C. Chung, H. –C. Lin, and Y. –T. Lin “A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 515-522, Feb. 2005.
[30] M. –K. Seo, S. –H. Sim, M. –H. Oh, H. –S. Lee, S. –W. Kim, I. –W. Cho, G. –H. Kim, and M. –G. Kim, “A 130-nm 0.9-V 66-MHz 8-Mb (256K X 32) local SONOS Embedded Flash EEPROM” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 877-883, Apr. 2005.
[31] M. –F. Chang, and S. –J. Shen, “A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 987-994, Mar. 2009.
[32] N. Otsuka and M. Horowitz, “Circuit techniques for 1.5-V power supply flash memory,” IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1217–1230, Aug. 1997.
[33] N. Verma, and A. P. Chandrakasan, “A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing” in ISSCC Dig. Tech. Papers, pp. 380-381, Feb. 2008.
[34] H. Chen, Course slides of Analog Integrated Circuits, NTHU, 2009
[35] S. Kajiyama, M. Fujito, H. Kasai, M. Mizuno, T. Yamaguchi, and Y. Shinagawa, “A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers” IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, Nov. 2008.
[36] B. Razavi, and Bruce A. Wooley, “Design Techniques for High-speed, High-Resolution Comparators” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.
[37] Y. –C. Lai and S. –Y. Huang “X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 1964-1971, Sep. 2008.
[38] T. Kumamoto, M. Nakaya, H. Honda, S. Asai, Y. Akasaka, and Y. Horiba “An 8-bit High-Speed CMOS A/D Converter” IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 976-982, Dec. 1986.
[39] X. Zhu1, Y. Chen1, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto and T. Kuroda1 “A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology” IEEE Custom Integrated Circuits Conference, 2008
[40] J. Javanifard, T. Tanadi, H. Giduturi, K. Loe, R. L. Melcher, S. Khabiri, N. T. Hendrickson, A. D. Proescholdt, D. A. Ward, and M. A. Taylor, “A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed” in ISSCC Dig. Tech. Papers, pp. 424-425, Feb. 2008.
[41] M. Bhargava1, M. P. McCartney, A. Hoefler, and Ken Mai, “Low-Overhead, Digital Offset Compensated, SRAM Sense Amplifiers” IEEE Custom Integrated Circuits Conference, 2009
[42] M. –J. Edward Lee, W. Dally, and P. Chiang “A 90 mW 4Gb/s equalized I/O circuit with input offset cancellation” in ISSCC Dig. Tech. Papers, pp. 252-253, Feb. 2000.
[43] H. –C. Lai, K.- Y. Cheng, Y. –C. King, and C. –J. Lin, “A 0.26-μm2 U-Shaped Nitride-Based Programming Cell on Pure 90-nm CMOS Technology” IEEE Electron Device Lett., vol. 28, no. 9, pp. 837–839, Sep. 2007.
[44] R. MIcheloni, L. Crippa, M. Sangalli, and G. Campardo, “The Flash Memory Read Path: Building Blocks and Critical Aspects” Proceedings of the IEEE, vol. 91, no. 4, pp. 537-553, Apr. 2003.
[45] D. Elmhurst, and M. Goldman, “A 1.8-V 128-Mb 125-MHz multi-level cell flash memory with flexible read while write”, in ISSCC Dig. Tech. Papers, pp. 286–287, Feb. 2003.
[46] D. Nobunaga1, E. Abedifard, F. Roohparvar, J. Lee, E. Yu, A. Vahidimowlavi, M. Abraham, S. Talreja, R. Sundaram, R. Rozman, L. Vu, C. - L. Chen, U. Chandrasekhar, R. Bains, V. Viajedor, W. Mak, M. Choi, D. Udeshi, M. Luo, S. Qureshi, J. Tsai, F. Jaffin, Y. Liu, and M. Mancinelli “A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throught and 200MB/s DDR Interface” , in ISSCC Dig. Tech. Papers, pp. 426–427, Feb. 2008.
[47] A. Worapishet, J. B. Hughes, and C. Toumazow “An Improved CMOS Offset-Compensated Current Comparator for High Speed Applications” in ISCAS Dig. Tech. Papers, pp. 535-538, 1998.
[48] C. –Y. Wu, and C. –C. Chen, and J. –J. Cho “A CMOS Transistor-Only 8-b 4.5-Ms/s Pipelined Analog-to-Digital Converter Using Fully-Differential Current-Mode Circuit Techniques” IEEE J. Solid-State Circuits, vol. 30, no. 5, pp. 522-532, May. 1995.
[49] H. Y. Yang, and R. Sarpeshkar “A Time-Based Energy-Efficient Analog-to-Digital Converter” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1590-1601, Dec. 2005.
[50] S. H. Kulkarni, Z. Chen, J. He, L. Jiang, M. B. Pedersen, and K. Zhang “A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 µm2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 863-868, Apr. 2010.
[51] N. Robson, J. Safran, C. Kothandaraman, A. Cestero, X. Chen, R. Rajeevakumar, A. Leslie, D. Moy, T. Kirihata, and S. Iyer “Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips” IEEE Custom Integrated Circuits Conference, 2007
[52] C. Kothandaraman, Sundar K. Iye,, and Subramanian S. Iyer “Electrically Programmable Fuse (eFUSE) using electromigration in silicides” IEEE Electron Device Letters, vol. 23, No. 9, pp. 523-525, Sep. 2002
[53] J. Safran, A. Leslie, G. Fredeman, C. Kothandaraman, A. Cestero, X. Chen, R. Rajeevakumar, D. –K. Kim, Y. Zuni Li, D. Moy, N. Robson, T. Kinhatal, and S. Iyer “A Compact eFUSE Programmable Array Memory for SOI CMOS” in Symp.VLSI Circuits Dig. Tech. Papers, pp. 72-73, Jun. 2007
[54] G. Uhlmann, T. Aipperspach, T. Kirihata, C., Kothandaraman, Y. Zun Li, C. Paone, B. Reed, N. Robson, J. Safran, D. Schmitt, S. Iyer “A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS” in ISSCC Dig. Tech. Papers, pp. 406–407, Feb. 2008.
[55] S. Chung, T. –W. Chung, P. –Y. Ker, and F. –L. Hsueh “A 1.25µm2 Cell 32Kb Electrical Fuse Memory in 32nm CMOS with 700mV Vddmin and Parallel/Serial Interface” in Symp.VLSI Circuits Dig. Tech. Papers, pp. 30-31, Jun. 2009
[56] S. Chung, J. –T. Huang, P. Chen, and F. –L. Hsueh “A 512x8 Electrical Fuse Memory with 15µm2 Cells Using 8-sq Asymmetric Fuse and Core Devices in 90nm CMOS” in Symp.VLSI Circuits Dig. Tech. Papers, pp. 74-75, Jun. 2009
[57] M. –F. Chang, S. –M. Yang, C. –W. Liang, C. –C. Chiang, P. –F. Chiu, K. –F. Lin, Y. –H. Chu, W. –C. Wu, and H. Yamauchi “A 0.29V Embedded NAND-ROM in 90nm CMOS for Ultra-Low-Voltage Applications” in ISSCC Dig. Tech. Papers, pp. 266–267, Feb. 2010.
[58] H. K. Cha, I. Yun, J. Kim, B. C. So, K. Chun, I. Nam, and K. Lee, “A 32-kB Standard CMOS Antifuse One-time Programmable ROM Embedded in a 16-bit Microcontroller,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2115–2124, Sep. 2006.
[59] R. S. C. Wang, R. S. J. Shen, and C. C. H. Hsu, “Neobit—High Reliable Logic Non-volatile Memory (NVM),” in Proc. IPFA, 2004, pp. 111–114.
[60] S. H Kulkarni, Z. Chen, J. He, L. Jiang, B. Pedersen, and K. Zhang “High-density 3-D metal-fuse PROM featuring 1.37µm2 1T1R bit cell in 32nm high-k metal-gate CMOS technology” in Symp.VLSI Circuits Dig. Tech. Papers, pp. 28-29, Jun. 2009
[61] R. Zeng, N. Chalagalla, D. Chu, D. Elmhurst, M. Goldman, C. Haid, A. Huq, T. Ichikawa, J. Jorgensen, O. Jungroth, N. Kajla, R. Kajley, K. Kawai, J. Kishimoto, A. Madraswala, T. Manabe, V. Mehta, M. Morooka, K. Nguyen, Y. Oikawa, B. Pathak, R. Rozman, T. Ryan, A. Sendrowski, W. Sheung, M. Szwarc, Y. Takashima, S. Tamada, T. Tanzawa, T. Tanaka, M. Taub, D. Udeshi, S. Yamada, and H. Yokoyama, “A 172 mm2 32Gb MLC NAND Flash Memory in 32nm CMOS” in ISSCC Dig. Tech. Papers, pp. 236–237, Feb. 2009

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