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研究生:陳建源
研究生(外文):Chen, Chien-Yuan
論文名稱:具有降低漏電流功能之熱感應奈米級靜態隨機存取記憶體
論文名稱(外文):A Thermal Aware Leakage Reduction Scheme for Nanometer-scale SRAM
指導教授:張孟凡
指導教授(外文):Chang, Meng-Fan
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:93
中文關鍵詞:靜態隨機存取記憶體漏電流熱感應低功率製程追蹤保持資料完整
外文關鍵詞:SRAMleakagethermal awarelow powerPVT trackingdata retention
相關次數:
  • 被引用被引用:0
  • 點閱點閱:246
  • 評分評分:
  • 下載下載:25
  • 收藏至我的研究室書目清單書目收藏:1
隨著製程演進至奈米時代,漏電流已成為不可忽略的問題,此外,靜態隨機存取記憶體的漏電流功率占了不少整合型系統晶片的功率耗,降低電源差對減少漏電流是十分有效的,在深次微米製程下,使用鉗地架構使得地電源線抬升對降低次臨界漏電流和閘極漏電流是常用的技巧,儘管如此,接面漏電流並沒有因此降低太多,因此,到了奈米製程,鉗頭架構使得頭電源線降低搭配浮接位元線已呈現一個趨勢因為次臨界漏電流、閘極漏電流和接面漏電流都能因此降低許多。
為了要節省甦醒時間和甦醒功率,我們混合了鉗地架構、鉗頭架構以及浮接位元線的技巧,此外,為了使得細胞內的資料不會流失,細胞的偏壓就必須小心設計,本論文中,我們提出了一個具有溫度警覺功能的偏壓架構而且兼顧了細胞穩定性即使製程、電壓和溫度變異發生時。我們提出了利用記憶體陣列中的一個複製欄來達到追蹤記憶體陣列的製程飄移以及溫度變異,且其額外的面積消耗和功率消耗都低於二個百分比。
一個由三萬兩千字元所組成的靜態隨機存取記憶體陣列使用了六五奈米互補金氧半技術製造來驗證我們的想法,量測結果顯示在高溫時我們能達到八十百分比的漏電流降低量,並且,使用我們提出架構的漏電流量測分布也比原先的漏電流分布來得窄。

Leakage has become pronounced as technology shrinks to nanometer scale. A large portion of SOC power dissipation directly comes from on-die SRAM leakage power. Low-er rail-to-rail voltage is an effective method to reduce SRAM array leakage. For deep sub-micron technology, footer is a common technique to raise the source line of pull-down NMOS and reduce both sub-threshold leakage and gate leakage. Nevertheless, junction leakage still remains and becomes worse for nanometer technology. Therefore, header combined with floating bit-lines becomes a trend to lower SRAM cell bias because it can reduce junction leakage aggressively. In order to save wake up time and wake up power, we use a hybrid clamping structure composed of footer, header, and floating bit-lines due to simultaneous wake up behaviors. Besides, it should be carefully controlled to maintain sufficient cell stability, avoiding potential data loss. In this work, we propose a thermal aware leakage reduction scheme and also concern the data retention issue with PVT varia-tion tracking. A 32kb SRAM macro has been fabricated in 65nm bulk CMOS technology to verify the idea of this work. The measurement results demonstrate that the SRAM array leakage achieves above 80% reduction at high temperature. In addition, SRAM array lea-kage distribution becomes narrower in our scheme compared to original one.
Abstract (Chinese) i
Abstract (English) ii
Acknowledgement (Chinese) iii
Contents iv
List of Figures vii
List of Tables xi
Acronyms xii
Chapter1 1
1.1 Motivation and Application for Low Leakage SRAM 1
1.2 Challenges of Nanometer-Scale SRAM 4
1.2.1 Process Variation 4
1.2.2 Drain Induced Barrier Lowering (DIBL) 5
1.2.3 Reverse Short Channel Effect (RSCE) 6
1.2.4 Negative Bias Temperature Instability (NBTI) 6
1.2.5 Static Noise Margin (SNM) 7
1.2.6 Write Margin (WM) 11
1.2.7 Bit-Line Leakage Issue 13
1.3 Thesis Organization 16
Chapter2 17
2.1 MOSFET Leakage Source 17
2.1.1 Sub-threshold Current 18
2.1.2 Gate-Induced Drain Leakage (GIDL) 21
2.1.3 Gate-Oxide Tunneling Current 23
2.1.4 Hot Carriers Injection Current 25
2.1.5 Reverse-Biased Junction BTBT Current 27
2.1.6 Punch-through Current 29
2.2 Temperature Dependency of Leakage 31
2.3 Leakage Source Distribution of SRAM Macro 32
Chapter3 34
3.1 Leakage paths in SRAM cell 34
3.1.1 Leakage Reduction Methods of Cell 35
3.2 Data Retention Issue 38
3.2.1 Data Retention Voltage (DRV) Analysis 38
3.3 Lower Cell Bias 44
3.3.1 Dynamic Voltage Scaling (DVS) 44
3.3.2 Power Gating Switches 45
3.3.3 Passive Sleep Control 50
3.3.4 Active Sleep Control 53
3.4 Header versus Footer during Sleep Mode 54
3.5 Body Control 56
Chapter4 58
4.1 Block diagram 58
4.2 Leakage Tracking Scheme (LTS) 60
4.3 Data Retention Scheme (DRS) 63
4.4 Combination of LTS and DRS 70
Chapter5 73
5.1 Architecture of Proposed SRAM 73
5.2 Test Chip Design 75
Chapter6 78
6.1 Measurement Results 78
6.2 Comparison and Conclusion of This Thesis 83
6.3 Future work 85
References 87

[1] P. Urard, "SoC Power-Reduction Techniques," ISSCC Tutorial 2008.
[2] S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T. Yoshihara, M. Igarashi, M. Takeuchi, H. Kawashima, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, and H. Shinohara, "A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 820-829, Apr. 2007.
[3] J. W. Tschanz, S. G. Narendra, Y. Ye, B. A. Bloechel, S. Borkar, and V. De, " Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1838-1845, Nov. 2003.
[4] K. Nii, Y. Tsukamoto, T. Yoshizawa, S. Imaoka, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino, and S. Iwade, "A 90-nm Low-Power 32-kB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile Applications," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 684-693, Apr. 2004.
[5] S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, B. Cherkauer, J. Stinson, J. Be-noit, R. Varada, J. Leung, R. D. Limaye, and S. Vora, "A 65-nm Dual-Core Mul-tithreaded Xeon® Processor," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 17-25, Jan. 2007.
[6] M. Yamaoka, Y. Shinozaki, N. Maeda, Y. Shimazaki, K. Kato, S. Shimada, K. Yanagisawa, and K. Osada, "A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 186-194, Jan. 2005.
[7] Y. Wang, H. J. Ahn, U. Bhattacharya, Z. Chen, T. Coan, F. Hamzaoglu, W. M. Hafez, C. H. Jan, P. Kolar, S. H. Kulkarni, J. F. Lin, Y. G. Ng, I. Post, L. Wei, Y. Zhang, K. Zhang, and M. Bohr, "A 1.1 GHz 12μA/Mb-leakage SRAM design in 65nm ultra-low-power CMOS technology with integrated leakage reduction for mobile application," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 172-179, Jan. 2008.
[8] S. J. Lee, K. C. Park, Y. H. Kim, Y. K. Hong, Y. You, K. R. Cho, T. W. Cho, and K. Eshraghian, "3D data compression and encryption for bio-medical health care monitoring and management system," in BioCAS Dig. Tech. Papers, pp. 161-164, Nov. 2009.
[9] S. Cosemans, W. Dehaene, and F. Catthoor, "A low power embedded SRAM for wireless applications," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1607-1617, Jul. 2007.
[10] International Technology Road Map for Semiconductors, 2005 edition.
[11] K. Puttaswamy, and G. H. Loh, "3D integrated SRAM components for high-performance microprocessors," IEEE Trans. Computers, vol. 58, no. 10, pp. 1369-1381, Oct. 2009.
[12] N. Weste and D. Harris., CMOS VLSI Design : A Circuits and Systems Perspective 3rd ed. Boston: Pearson/Addison-Wesley, 2005.
[13] H. Yamauchi, "Variation-Tolerant SRAM Circuit Designs," ISSCC Tutorial 2009.
[14] J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V. De, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1396-1402, Nov. 2002.
[15] A. J. Bhavnagarwala, S. Kosonocky, C. Radens, C. Yuen, K. Stawiasz, U. Srinivasan, S. P. Kowalczyk, and M. M. Ziegler, "A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 946-955, Apr. 2008.
[16] S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, "Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1370-1382, Jun. 2007.
[17] N. N. Mojumder, S. Mukhopadhyay, J. J. Kim, C. T. Chuang, and K. Roy, " Self-Repairing SRAM Using On-Chip Detection and Compensation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 1, pp. 75-84, Jan. 2010.
[18] K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Purta, A. Nishida, S. Kamohara, and T. Hiramoto, "Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies," in IEDM Dig. Tech. Papers, pp. 467-470, Dec. 2007.
[19] J. Chen, L. T. Clark, and T. H. Chen, "An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2344-2353, Oct. 2006.
[20] J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007.
[21] B. H. Calhoun, and A. P. Chandrakasan, "A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation," IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 680-688, Mar. 2007.
[22] T. H. Kim, J. Liu, J. Keane, and C. H. Kim, "A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 518-529, Feb. 2008.
[23] N. Verma, and A. P. Chandrakasan, "A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141-149, Jan. 2008.
[24] B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2338-2348, Oct. 2008.
[25] I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, "A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650-658, Feb. 2008.
[26] T. H. Kim, J. Keane, H. Eom, and C. H. Kim, " Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 7, pp. 821-829, Jul. 2010.
[27] K. Kang, S. P. Park, K. Roy, M. A. Alan," Estimation of Statistical Variation in Temporal NBTI Degradation and its Impact on Lifetime Circuit Performance," IEEE Trans. International Conf. Computer-Aided Design (CAD), vol. 15, no. 11, pp. 730-734, Nov. 2007.
[28] H. Yamauchi, "Embedded SRAM Design in Nanometer-Scale Technologies," in Embedded Memories for Nano-Scale VLSIs, K. Zhang, Ed., 1st ed Boston, MA: Springer-Verlag US, 2009, pp. 39-88.
[29] E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. 22, no. 5, pp. 748-754, Oct. 1987.
[30] E. Grossar, M. Stucchi, K. Maex, and W. Dehaene, "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, Nov. 2006.
[31] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, "A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146-151, Jan. 2006.
[32] K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe, S. Okazaki, K. Satomi, H. Akamatsu, and H. Shinohara, "A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 180-191, Jan. 2008.
[33] M. Yamaoka, R. Tsuchiya, and T. Kawahara, " SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2366-2372, Nov. 2006.
[34] M. Khellah, N. S. Kim, Y. Ye, D. Somasekhar, T. Karnik, N. Borkar, G. Pandya, F. Hamzaoglu, T. Coan, Y. Wang, K. Zhang, C. Webb, and V. De, " Process, Temperature, and Supply-Noise Tolerant 45 nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1199-1208, Apr. 2009.
[35] H. Nho, P. Kolar, F. Hamzaoglu, Y. Wang, E. Karl, Y. G. Ng, U. Bhattacharya and K. Zhang, " A 32nm High-κ Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation," ISSCC Dig. Tech. Papers, pp. 346-347, Feb. 2010.
[36] M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, "90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 705-711, Mar. 2006.
[37] K. Roy, S. Mukhopadhyay, and H. M. Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
[38] N. N. Mojumder, K. Roy, "Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories," IEEE Trans. Electron Devices, vol. 56, no. 10, pp. 2193-2201, Oct. 2009.
[39] A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C. H. Kim, " Leakage Power Analysis and Reduction for Nanoscale Circuits," Proceedings of the IEEE, vol. 26, no. 3, pp. 68-80, Mar. 2006.
[40] K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, "16.7fF/Cell Tunnel-Leakage-Suppressed 16-Mb SRAM for Handing Consmic-Ray-Induced Multi-errors," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1952-1957, Mar. 2003.
[41] C. H. Kim, J. J. Kim, S. Mukhopadhyay, and K. Roy, "A Forward Body-biased Low-leakage SRAM Cache Device, Circuit and Architecture Considerations," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 3, pp. 349-357, Mar. 2005.
[42] A. Agarwal, Hai. Li, and K. Roy, "DRG-Cache: A Data Retention Gated-Ground Cache for Low Power," in Design Automation Conference (DAC) Dig. Tech. Papers, pp. 473-478, Jun. 2002.
[43] H. Yamauchi, T. Iwata, H. Akamatsu, and A. Matsuzawa, "A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme," in Symp.VLSI Circuits Dig. Tech. Papers, pp. 126-127, Jun. 1996.
[44] S. Cserveny, L. Sumanen, J. M. Masgonty, and C. Piguet, "Locally Switched and Limited Source-Body Bias and Other Leakage Reduction Techniques for a Low-Power Embedded SRAM," IEEE Trans. Circuits and Syst. II, vol. 52, no. 10, pp. 636-640, Aug. 2005.
[45] A. Nourivand, C. Wang, and M. O. Ahmad, "An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAMs," in ISCAS Dig. Tech. Papers, pp. 2790-2793, May 2007.
[46] M. Sharifkhani and M. Sachdev, "A Low Power SRAM Architecture Based on Segmented Virtual Grounding," in Symp. Low Power Electronics and Design Conf. (ISLPED), pp. 256-261, Oct. 2006.
[47] A. J. Bhavnagarwala, A. Kapoor, and J. D. Meindl, "Dynamic-threshold CMOS SRAM’s for fast, portable applications," in Proc. ASIC/SOC Conf., pp. 359–363 2000.
[48] H. Kawaguchi, Y. Itaka, and T. Sakurai, "Dynamic leakage cutoff scheme for low-voltage SRAM’s," in Proc. Symp. VLSI Circuits Dig. Tech. Papers, pp. 140-141, Jun. 1998.
[49] C. H. Kim and K. Roy, "Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors," in Proc. Int. Symp. Low Power Electronics and De-sign Conf. (ISLPED), pp. 251–254, Oct. 2002.
[50] N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, "Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 167-184, Feb. 2004.
[51] F. Hamzaoglu, K. Zhang, Y. Wang, H. J. Ahn, U. Bhattacharya, Z. Chen, Y. G. Ng, A. Pavlov, K. Smits, and M. Bohr, "A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 148-154, Jan. 2009.
[52] F. R. Saliba, H. Kawaguchi, and T. Sakurai, "Experimental Verification of Row-by-Row Variable VDD Scheme Reducing 95% Active Leakage Power of SRAM’s," in Proc. Symp. VLSI Circuits Dig. Tech. Papers, pp. 162-165, Jun. 2005.
[53] Y. Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y. G. Ng, L. Wei, Y. Zhang, K. Zhang, and M. Bohr, "A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 103-110, Jan. 2010.
[54] K. Itoh, A. R. Fridi, A. Bellaouar, and M. I. Elmasry, "A Deep Sub-V, Single Pow-er-supply SRAM Cell with Multi-Vt, Boosted Storage Node and Dynamic Load," in Proc. Symp. VLSI Circuits, pp. 132-133, Jun. 1996.
[55] C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A forward body biased low-leakage SRAM cache: Device and architecture considerations," in Proc. Int. Symp. Low Power Electronics and Design (ISLPED), pp. 6-9, Aug. 2003.
[56] H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, "SRAM Leakage Suppression by Minimizing Standby Supply Voltage," in Proc. Int. Symp. Quality Electronic and Design (ISQED), pp. 55-60, 2004.
[57] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice-Hall 2002.
[58] M. E. Sinangil, N. Verma, and A. P. Chandrakasan, "A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3163-3173, Nov. 2009.
[59] A. Agarwal, K. Roy, "A Noise Tolerant Cache Design to Reduce Gate and Sub-threshold Leakage in the Nanometer Regime," in Symp. Low Power Electronics and Design Conf. (ISLPED), pp. 18-21, Oct. 2003.
[60] Y. Takeyama, H. Otake, O. Hirabayashi, K. Kushida, and N. Otsuka, "A Low Leakage SRAM Macro With Replica Cell Biasing Scheme," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 815-822, Apr. 2006.
[61] J. Chang, M. Huang, J. Shoemaker, J. Benoit, S. L. Chen, W. Chen, S. Chiu, R. Ganesan, G. Leong, V. Lukka, S. Rusu, and D. Srivastava, "The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 846-852, Apr. 2007.
[62] C. H. Kim, J. J. Kim, I. J. Chang, and K. Roy, "PVT-Aware Leakage Reduction for On-Die Caches With Improved Read Stability," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 170-178, Jan. 2006.
[63] M. Khellah, D. Somasekhar, Y. Ye, N. S. Kim, Member, J. Howard, G. Ruhl, M. Sunna, J. Tschanz, N. Borkar, F. Hamzaoglu, G. Pandya, A. Farhang, K. Zhang, and V. De, "A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 233-242, Jan. 2007.
[64] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and Mark Bohr, "SRAM Design on 65-nm CMOS Technology With Dynamic Sleep Transistor for Leakage Reduction," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 895-901, Apr. 2005.
[65] T. H. Kim, J. Liu, and C. H. Kim, "A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode," IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1785-1795, Jun. 2009.
[66] S. Ghosh, S. Mukhopadhyay, K. Kim, and Kaushik Roy, "Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled SRAM," in Design Automation Conference (DAC) Dig. Tech. Papers, pp. 971-976, Jun. 2006.
[67] Jui-Jen Wu, Yen-Huei Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, and Hiroyuki Yamauchi, "A Large σVTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme," in Symp.VLSI Circuits Dig. Tech. Papers, pp. 103-104, Jun. 2010.

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1. 鄭明娳 〈受傷的戀土情節—評陳冠學《訪草》〉《聯合文學》 5 卷53 期 1989
2. 鄭穗影 〈《田園之秋》的政治傾向初探〉《文學界》28 期1989年11月
3. 王汎森〈「心即理」說的動搖與明未清初學風之轉變〉,《中央研究院歷史語言研究所集刊》,第六十五本第二分,1994年6月,頁333-373。
4. 王家儉〈清代禮學的興與經世禮學思想的流變〉,《漢學研究》第24卷第1期,2006年6月,頁269-294。
5. 王汎森〈清初思想中形上玄遠之學的沒落〉,《中央研究院歷史語言研究所集刊》,第六十九本第三分,1998年9月,頁557-587。
6. 郭漢辰 〈那個午后,聆聽散文大師陳冠學半世紀的文學堅持〉《文化生活》8
7. 鄭穗影 <吾友陳冠學先生>《文學界》7期1983年8月
8. 鄭穗影 〈吾友陳冠學先生〉《文學界》7 期1983 年8 月
9. 林正三 〈陳冠學的美夢〉《德明學報》25期2005年6月
10. 魏元珪 〈老莊哲學的自然觀與環保心靈〉《哲學雜誌》13期1995年7月
11. 王家歆 〈田園真意—讀陳冠學《田園之秋》〉《書評》10期1994年6月
12. 謝政諭 〈道家思想與後現代社會環境倫理〉《東吳政治學報》 2期1993年3
13. 丘為君〈清代思想史「研究典範」的形成、特質與義涵〉,《清華學報》新廿四卷第四期,1994年12月,頁451-494。
14. 古清美〈清初經世之學與東林學派之關係〉,《孔孟月刊》第二四卷第三期,1985年11月,頁44-51。
15. 何佑森〈明末清初的實學〉,台北:《臺大中文學報》第四期,1991年6月,頁37-51。