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研究生:吳國立
研究生(外文):Wu, Kuo-Li
論文名稱:考慮製程變異下在後矽根據診斷技術結果調整電壓之方法
論文名稱(外文):A Post-Silicon Voltage-tuning Methodology for Process Variation based on Diagnosis Results
指導教授:劉靖家
指導教授(外文):Liou, Jing-Jia
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:51
中文關鍵詞:製程變異可調式電路提升良率診斷
外文關鍵詞:Process VariationCell-based Tunable CircuitIncreasing Yielddiagnosis
相關次數:
  • 被引用被引用:0
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  • 下載下載:9
  • 收藏至我的研究室書目清單書目收藏:0
當半導體的製程技術進入奈米等級後,製程變異 (Process varaition) 的影響越來越嚴重,導致晶片的良率持續地惡化。近年來,許多後矽調整技術廣泛的被運用,藉由增加功率消耗來補償失敗晶片的變異。在「1」論文中,作者提出了一套以列電壓調控為基礎的可調式電路設計機制 (row-based tunable design),此機制允許使用者可以逐列地調整工作電壓 (supply voltag)。在可調整電路中,供給電壓(VDD)與接地電壓(GND)皆可以相較於正常電壓調整+/-0.2伏,也就是說每一個電壓都有三種值。所以在本篇論文中,我們提出了一套考慮製程變異下根據診斷技術結果來做電壓調整的機制,可增加部分電路的速度或是降低動態功率消耗。首先,由量測結果可得知失敗的晶片,再藉由論文「2」的診斷技術可得到晶片的時脈資訊。最後根據診斷的結果做VDD和GND電壓調整,讓修正過後的晶片符合我們所需的規格。
  在實驗方面,本論文的電路採用180奈米製程技術。本實驗以調整整顆晶片電壓方法(Full-chip tuning)來做比對。在s38584中,我們的方法在加入不同的時脈延遲下動態消耗功率分佈在-3.07%到24.41%間,調整整顆晶片動態消耗功率分佈在0%到49.43%間,節省的動態功率可以達25%。在b17中,節省的動態功率可以達30%。由上實驗我們可以知道,越大的電路可以讓動態功率消耗節省越多、良率越高。本論文提出的演算法不僅可以有效地修正失敗的晶片且可以節省功率消耗。
Process variation become increasingly serious as the semicondouctor technology keeps advancing
toward nanometer scales. Recently, several post silicon tuning techniques have been widely
used to compensate the variation of failing chips, though at the cost of increasing power consumption.
In [1],the authors proposed a row-based tunable design methodology which allows users to
fine-tune the supply voltages of manufactured chips. In this tunable circuits, the supply voltage
(VDD) and ground voltage (GND) can be adjusted up to +/- 0.2 Volt over the nominal voltage
respectively, e.g. the voltage level of each cell could have three possibilities. So we proposed a
post-silicon voltage tuning methodology for process variation based on diagnosis results by this
tunable circuit, which we can selectively tune up the voltages to increase the speed of parts of the
circuits or tune them down to save power. First, once a chip was found failure by delay testing.
Then we will use the diagnosis process [2] to get timing data of the chip. Finally, use voltage assignment
program [3] to adjust VDD and GND by row to fix the timing violation which is affected
by process variation.
In the experiments, we have applied our method on circuit under 180nm process node and
compare with the full chip tuning method. In s38584, the range of dynamic power overhead is
-3.07% to 24.41% compared to a typical voltage assignment case by our method. And the range
of dynamic power overhead is 0% to 49.43% compared to a typical voltage assignment case by
full-chip tuning. We can saving as high as 25% of dynamic power by our method. And in b17, we
can save as high as 25% of dynamic power by out method. The proposed algorithm can not only
effectively fix failed chip in timing but reduce the power consumption.
1 Introduction 7
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Overview of the Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.2 Preview of Our Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Background 12
2.1 Reviews of Tunable Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Adopted Tunable Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Voltage Assignment Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Diagnosis Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Voltage Tuning Methodology based on Diagnosis Results 22
3.1 Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Proposed Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Calculate Tunable Circuit Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Diagnosis Method to Estimate Cell Delay . . . . . . . . . . . . . . . . . . . . . . 27
3.5 Voltage Tuning Methodology based on Diagnosis Result . . . . . . . . . . . . . . 28
4 Experimental Setups – Chip Sampling 32
4.1 Objectives of Chip Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 Vt Variation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3 Process Variation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 Process Variation Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 36
4.5 Full chip tuning algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Experimental Results 39
5.1 Experimental Results on Different Benchmarks . . . . . . . . . . . . . . . . . . . 39
5.2 Experimental Results of Different Amount of Variation . . . . . . . . . . . . . . . 42
5.2.1 Fixing Area with Process Variation . . . . . . . . . . . . . . . . . . . . . 42
5.2.2 Increasing Area with Process Variation . . . . . . . . . . . . . . . . . . . 42
5.3 The Experimental Results of Yield . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6 Conclusions and Future Work 48
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
[1] M. Chun-Chia Chen, “Design Methodology and Simulation Framework for Variation-Aware Cell-based Tunable Circuits,” 2008.
[2] P. Ying-Yen Chen, “Delay Fault Diagnosis Techniques Targeting on Both Spot Delay Defects and Systematic Process Variations,” 2009.
[3] M. Chung-Yen Chien, “A Post-Silicon Voltage-tuning Algorithm for Increasing Performance Yield under Power Constraints,” 2009.
[4] M. Choi and L. Milor, “Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing,” IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1350–1367, 2006.
[5] M. Eisele, J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf, “The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 4, pp. 360–368, 1997.
[6] K. Bowman, S. Duvall, and J. Meindl, “Impact of die-to die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” IEEE Journal of Solid-State Circuits, vol. 37, no. 2, pp. 183–190, 2002.
[7] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variations and impact on circuits and microarchitecture,” ACM/IEEE Design Automation Conference, pp. 338–342, 2003.
[8] K. Usami and M. Horowitz, “Clustered voltage scaling technique for low-power design,” Proceedings of the 1995 international symposium on Low power design, pp. 3–8, 1995.
[9] K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanzawa, M. Ichida, and K. Nogami, “Automated low-power technique exploiting multiple supply voltagesapplied to a media processor,” IEEE Journal of Solid-State Circuits, vol. 33, no. 3, pp. 463–472, 1998.
[10] D. Lackey, P. Zuchowski, T. Bednar, D. Stout, S. Gould, J. Cohn, I. Div, and V. Essex Junction, “Managing power and performance for system-on-chip designs using Voltage Islands,” IEEE/ACM International Conference on Computer Aided Design, pp. 195–202, 2002.
[11] J. Carballo, J. Burns, S. Yoo, I. Vo, and V. Norman, “A semi-custom voltage-island technique and its application to high-speed serial links,” Proceedings of the international symposium on Low power electronics and design, pp. 60–65, 2003.
[12] J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu, “Architecting Voltage Islands in Core-Based System-on-a-Chip Designs,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 180–185, 2004.
[13] H. Wu, I. Liu, M. Wong, and Y. Wang, “Post-placement voltage island generation under performance requirement,” IEEE/ACM International Conference on Computer-Aided Design, pp. 309–316, 2005.
[14] H. Wu, M. Wona, and I. Liu, “Timing-constrained and voltage-island-aware voltage assignment,” ACM/IEEE Design Automation Conference, pp. 429–432, 2006.
[15] B. Liu, Y. Cai, Q. Zhou, and X. Hong, “Power driven placement with layout aware supply voltage assignment for voltage island generation in dual Vdd designs,” Asia and South Pacific Conference on Design Automation, p. 6, 2006.
[16] L. Guo, Y. Cai, Q. Zhou, and X. Hong, “Logic and Layout Aware Voltage Island Generation for Low Power Design,” Asia and South Pacific Conference on Design Automation, pp. 666–671, 2007
[17] A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, “Statistical delay computation considering spatial correlations,” pp. 271–276, 2003.
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