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研究生:陳欣沅
研究生(外文):Chen, Hsin-Yuan
論文名稱:MultiModuleDiminished-OneMultipliersDesign
論文名稱(外文):多模數之基數減1乘法器設計
指導教授:張慶元張慶元引用關係
指導教授(外文):Chang, Tsin-Yuan
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:62
中文關鍵詞:負數乘法器基數減1多模數
外文關鍵詞:negativemultiplierdiminished-1multi module
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近年來,基數減1的模組(2n+1) 乘法器,有許多種做法。在此論文裡,我提出了一種新做法,專門針對基數減1的模組(2n+1) 乘法器,並且衍生出其它電路。
本論文提出2種一系列餘數乘法器,第一種應用在模數(2n+1),比較於前人作法,在數據方面比較優良,並且不需要特別做偵測真實零的電路。
第二種是改良第一種,可以整合5種模數(2n+1),2n,(2n-1),(2n+1+1),(2n+11),利用加一些多工器,分工器,及少許電路,即可整合5種模數之餘數乘法器。
基本構想就是利用減法,這個理論不只可以用來表示基數減1的模數(2n+1) 乘法器,進而達到減少面積與功率上的消耗,更可以利用硬體共用之做法,來選擇模組(2n-1) 與2n與(2n+1-1)普通乘法器,更能產生過往作法不能產生的模數(2n+1+1)的基數減1乘法器,也就是可切換式多模數乘法器,還能夠節省偵測真實零的硬體電路消耗。

誌謝…………………………………………………………………. ii
中文摘要…………………………………………………………..... iii
List of Contents……………………………………………………... IV
List of Figures……………………………………………………… VI
List of Tables……………………………………………………….. VII
Chapter 1. 介紹………………………………………………….. 1
1.1 動機與RNS基礎流程介紹……………………….................. 1
1.2 動機與研究故事…………………..………………………….. 3
1.3 論文大綱……………………………………………................. 4
Chapter 2. 運算與架構……………………………….…………... 5
2.1 Wallice與Dadda 演算法的運算區別與討論………..……… 5
2.2 餘數乘法器中全加減器的實現………………….………….. 6
2.3 餘數乘法器的實現(即非基數減1)………………………….. 10
2.4 套用Wallice 演算法的基數減1之2n+1餘數乘法器………... 13
2.5 套用Dadda 的基數減1之2n+1餘數乘法器…………………. 17
Chapter 3. 改善公式,架構,與規則性之推導及應用…............ 20
3.1 加減法器之實現……………………………………………… 20
3.2 針對2n+1的基數減1之餘數乘法器…………………………. 21
3.3 多共用模數的基數減1之2n+1餘數乘法器………………….. 25
3.4 負數規則性與推導…………………………………………….. 29
3.5 可變換式的多模數乘法器(Multi-Modulo Multiplier)………… 40
3.6 Detection bit說明……………………………………………… 48
Chapter 4. 數據比較……………………………………………….. 53
4.1 Using strict delay constraints…………………………………… 53
Chapter 5. 結論…………………………………………………… 55
Reference ……………………………………………………… 60

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