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研究生:游智威
研究生(外文):You, Jhih-Wei
論文名稱:應用敏感度分析於三維晶片內穿矽連接孔之特性研究
論文名稱(外文):Performance Characterization of TSV in 3D IC via Sensitivity Analysis
指導教授:黃錫瑜黃錫瑜引用關係
指導教授(外文):Huang, Shi-Yu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:50
中文關鍵詞:穿矽連接孔三維晶片環型震盪器敏感度分析
外文關鍵詞:Through Silicon Via3D ICoscillation ringsensitivity analysis
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  • 下載下載:9
  • 收藏至我的研究室書目清單書目收藏:0
在現今製程技術不斷的進步下,一有限平面內所能擺放的電晶體個數終將因達到各元件所能容忍的最小尺寸而趨於飽和。三維晶片(3D IC)被認為可以有效的解決此一問題,透過在垂直方向堆疊多個平面藉以增加面積來給電晶體擺放。而這些垂直排列且互相平行的平面則是利用一種稱作穿矽連接孔(Through Silicon Via, TSV)的橋樑來進行彼此間的溝通。在製程上由於穿矽連接孔的良率不佳,致使三維晶片的總體良率下降,因此為了增進三維晶片的良率,我們有必要針對穿矽連接孔進行一連串的研究與測試,包含除錯、修復、建立其在真實晶片內延遲時間的分佈情況……等。
在這篇論文中,我們提出了一個方法能測出在三維晶片內穿矽連接孔的延遲時間。我們採用了振盪環的概念,利用一些周邊電路與一對穿矽連接孔來形成一個振盪環。以此為基礎,我們使用了稱之為敏感度分析的方法來進一步推導出在振盪環裡每一根穿矽連接孔的延遲時間。我們藉由調控這二根穿矽連接孔驅動端的驅動力道來使振盪環振出來的週期發生改變,接著我們再量測這些變動量並經由一些分析來得出每一根穿矽連接孔的延遲時間。我們同時也提出測量多對穿矽連接孔的方法,此種方法能夠解決在測試中需要同步訊號的問題。最後藉由蒙地卡羅分析法,在30%的電晶體通道寬度變動與繞線長度的變化下,我們的方法仍能保有平均2%的誤差。以及當我們在預估穿矽連接孔的電容時,我們的不準確度在8%以內。

In this thesis, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation ring test, in which two TSVs are connected with some peripheral circuits to form an oscillation ring. Upon this foundation, we propose a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in the oscillation ring - a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring’s period. By some following analysis, the propagation delay of each TSV can be revealed. In addition to two TSVs to be characterized, we also present lots of TSVs characterization scheme to avoid the synchronous issue. Monte-Carlo analysis of a typical TSV with 30% width variation of transistors and routing wires variation occurring shows that characterization error of this method is average within 2% and the prediction of the capacitances of TSVs within 8%.
Abstract……………………………………………………………………………… I
Contents…………………………………………………………………………..... IV
List of Figures…………………………………………………………………….... VI
List of Tables……………………………………………………………………... VIII
Chapter 1 Introduction................................................................................................. 1
1.1 Motivation……………………………………………………………. 3
1.2 Thesis Organization………………………………………………….. 4
Chapter 2 Preliminary……………………………………………………………….. 5
2.1 Delay Measurement Methods and Testing……..…………………….. 5
2.1.1 Directly Delay Measurement [17]…………………………….. 5
2.1.2 Indirectly Delay Measurement [6]……………………………. 6
2.1.3 Oscillation Ring Test for Delay Fault………………………… 9
2.2 TSV Testing before Bonding………………………………………... 10
Chapter 3 Sensitivity Analysis with TSV Delay…………………………………… 12
3.1 TSV Equivalent Resistance and Capacitance Model (RC Model)….. 12
3.2 TSV Delay Estimation………………………………………………. 15
3.3 Sensitivity Analysis…………………………………………………. 16
Chapter 4 Proposed Architecture of TSV Performance Characterization………….. 19
4.1 The Driver with Changeable Driving Strength……………………... 19
4.2 The Method to Produce △TA→B……………………………………. 20
4.3 The Architecture of Oscillation Ring (OR)…………………………. 22
4.3.1 Traditional Oscillation Ring…………………………………. 22
4.3.2 Modified Oscillation Ring…………………………………… 24
4.3.3 The Whole Circuit and Operations of Test Unit……………... 25
4.4 ΔT-to-TSV-delay Dictionary………………………………………. 27
4.5 Characterization Flow of One Pair of TSVs…………………........... 29
4.6 The Advantages of Sensitivity Analysis…………..………………… 30
4.7 Characterization of Lots TSVs……………………………............... 31
4.8 The Area Overhead of Test Unit and Local Control Units…………. 35
Chapter 5 Simulation Results……...………………………………………………. 37
5.1 Variation Analysis…………………………………………............... 37
5.2 The Variation Environment and TSV Model Used in Simulation….. 39
5.3 The Simulation Results with Variation Environments……………… 41
Chapter 6 Conclusions………...…………………………………………………… 46
Bibliography……………………………………………………………………….. 47

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[2]. K. Arabi, H. Ihs, C. Dufaza and B. Kaminska, “Digital Oscillation-Test Method for Delay and Stuck-at Fault Testing of Digital Circuits,” in Proc. of International Test Conference, pp. 91-100, 1998.

[3]. A. Bassi, A. Veggetti, L. Croce, and A. Bogliolo, “Measuring the Effects of Process Variations on Circuit Performance by Means of Digitally Controllable Ring Oscillators,” in Proc. of Microelectronic Test Structures, pp. 214-217, March 2003.

[4]. P. Y. Chen, C. W. Wu, and D. M. Kwai, “On-Chip TSV Testing for 3D IC Before Bonding Using Sense Amplification,” in Proc. of IEEE Asian Test Symposium, pp. 450-455, Nov. 2009.

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[6]. B. P. Das, B Amrutur, H.S. Jamadagni, N.V. Arvind, and V. Visvanathan, “Within-Die Gate Delay Variability Measurement Using Re-Configurable Ring Oscillator,” in Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp.133-136, Sep. 2008.

[7]. L. S. Dutta and T. Hillmann-Ruge, “Application of Ring Oscillators to Characterize Transmission lines in VLSI Circuits,” IEEE Trans. on Components, Packaging, Manufacturing Technology, vol. 18, no. 4, pp. 651–657, Nov. 1995.

[8]. A. B. Kahng and S. Muddu, “Efficient Gate Delay Modeling for Large Interconnect Loads,” in proc. of IEEE Multi-Chip Module Conference (MCMC), pp. 202-207, 1996.

[9]. D. Khalil, Y. Ismail, M. Khellah, T. Karnik, and V. De, “Analytical Model for the Propagation Delay of Through Silicon Vias,” in Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 553-556, 2008.

[10]. K. S.-M. Li, C. L. Lee, C. Su, and J. E. Chen, “Oscillation Ring Based Interconnect Test Scheme for SoC,” in Proc. of IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. 184–187, 2005.

[11]. I. Loi, S. Mitra, T. H. Lee, S. Fujita, and L. Benini. “A Low-Overhead Fault Tolerance Scheme for TSV-Based 3D Network on Chip Links,” in Proc. of International Conference on Computer-Aided Design, pp. 598–602, Nov. 2008.

[12]. J.-Q. Lu, K. Rose, and S. Vitkavage, “3D Integration: Why, What, Who, When?” Future Fab International (http://www.future-fab.com/), pp. 25-27, July 2007.

[13]. E. J. Marinissen and Y. Zorian, “Testing 3D Chips Containing Through-Silicon Vias,” in Proc. of International Test Conference, pp.1-11, 2009.

[14]. P. R. O’Brien and T. L. Savarino, “Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation,” in Proc. of Design Automation Conference, pp. 512–515, Nov. 1989.

[15]. I. Savidis and E. G. Friedman, “Closed-Form Expressions of 3-D Via Resistance Inductance, and Capacitance,” IEEE Transactions on electron devices, vol. 56, No.9, Sep. 2009

[16]. S. Spiesshoefer, Z. Rahman, G. Vangara, S. Polamreddy, S. Burkett, and L. Schaper, “Process Integration for Through-Silicon Vias,” Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, vol. 3, issue 4, pp. 824-829, 2005.

[17]. C. C. Su, Y. T. Chen, M. J. Huang, G. N. Chen, and C. L. Lee, “All Digital Built-In Delay and Crosstalk Measurement for On-Chip Buses,” in Proc. of Design, Automation & Test in Europe Conference and Exhibition (DATE), pp. 527-531, March 2000.

[18]. W. C. Wu, C. L. Lee, M. S. Wu, J. E. Chen, and M. Abadir, “Oscillation Ring Delay Test for High Performance Microprocessor,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 16, no. 1-2, pp. 147-155, 2000.

[19]. H. Yan and A. D. Singh, “A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects,” in Proc. of 18th International Conference on VLSI Design, pp. 47-52, Jan. 2005.

[20]. B. Zhou and A. Khouas, “Measurement of Delay Mismatch Due to Process Variations by Means of Modified Ring Oscillators,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 5, pp. 5246-5249, May 2005.

[21]. N. H. E. Weste, D. Harris, “CMOS VLSI Design A Circuits and Systems Perspective Third Edition”, Addison Wesley, 2004.

[22]. TSMC 0.18μm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook.






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