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研究生:鄭智文
研究生(外文):Cheng, Chih-Wen
論文名稱:應用於低功率內嵌式動態隨機存取記憶體之溫度察覺自我刷新控制方案
論文名稱(外文):Temperature-Aware Self-Refresh Control Scheme for Low Power Embedded-DRAM
指導教授:張孟凡
指導教授(外文):Chang, Meng-Fan
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:94
中文關鍵詞:漏電流內嵌式動態隨機存取記憶體自我刷新溫度察覺低功率
外文關鍵詞:leakageEmbedded-DRAMself-refreshtemperature awarelow power
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由於成本效益比靜態隨機存取記憶體高以及隨機存取速度比快閃記憶體更為快速的優點,嵌入式動態隨機存取記憶體被廣泛應用於多數的電子產品當中。然而對於系統單晶片而言,持續上升的功率消耗是一個存在的大問題。因此低功率消耗的研究議題應該要被考慮到晶片設計當中。對於內嵌式動態隨機存取記憶體而言,利用傳統制訂的自我刷新週期是為了要確保已經寫入的資料能夠被完整地保存於記憶胞陣列當中。但也因此當處於室溫狀況的時候,記憶胞的資料保存時間將可以比高溫環境下的保存時間還要能夠延伸至更久。因此在室溫的情況下,利用傳統的自我刷新週期將會有額外的資料保存功率消耗。
為了能夠降低在較為低溫狀況時的資料保存功率消耗,我們提出了溫度察覺自我刷新方案有效地去延長資料保存週期。藉由針對複製的記憶胞陣列做離散時間且動態的追蹤,以達成在不同的溫度下可以利用二的次方之運算方式去延長原先規格所制定的自我刷新週期。
最後我們提出的溫度察覺自我刷新方案,以六十五奈米內嵌式動態隨機存取記憶體且低漏電的製程技術和一個由八百萬字元(8Mb)所組成的內嵌式動態隨機存取記憶體電路建構在一起。量測結果顯示對於資料保存功率損耗的交流部分,於室溫下的環境下可以節省高達百分之九十五點九二的功率損耗。
Embedded-DRAMs are widely used in many electronic products due to its more cost-effective than SRAM and its faster read/write random access than FLASH. However, increasingly large power consumption is a big problem in SOC system. For this reason, low power design issue should be taken into consideration. For embedded-DRAM, the stored data should be confirmed to retain in cell array with conventional period in self-refresh mode. But at room temperature, the cell data retention time will extend much longer than that in higher temperature condition. Thus, there is an additional AC component of data retention power at room temperature with conventional period.
To solve this problem, we propose a temperature-aware self-refresh control scheme to extend self-refresh period in lower temperature condition. By using discrete-time dynamic tracking to detect replica cell array, conventional self-refresh period can be extended by power function of two with various temperatures.
We apply our design in 65nm EDRAM low leakage process within an 8Mb eDRAM macro. The experiment results show that, 95.92% reduction of AC component of data retention power can achieve at room temperature.
Contents
Abstract (Chinese)
Abstract (English)
Acknowledgements (Chinese)
Contents i
List of Figures iv
List of Tables ix
Chapter 1 Introduction 1
1.1 Low Power Embedded-DRAM Applications 1
1.2 Challenges of Low Power Embedded-DRAM 3
1.3 Basic Operations of DRAM 4
1.3.1 Read Operation 5
1.3.2 Write Operation 6
1.3.3 Refresh Operation 7
1.4 Structure of This Thesis 8
Chapter 2 Leakage and Temperature Dependency 10
2.1 MOSFET Leakage Mechanisms 10
2.1.1 Sub-threshold Current (I1) 11
2.1.2 Gate-Induced Drain Leakage (I2) 13
2.1.3 Gate-Oxide Tunneling Current (I3) 15
2.1.4 Hot carrier injection Current (I4) 17
2.1.5 Reverse-Biased Junction BTBT Current (I5) 19
2.1.6 Punch-Through Current (I6) 20
2.2 Leakage with Temperature Dependency 21
Chapter 3 Design Issues in Low Power Self-Refresh Mode 23
3.1 Cell data retention 23
3.1.1 Cell Structure 23
3.1.2 Data Retention Time 27
3.2 Power Consumption 30
3.3 Conventional Self-Refresh Mode 31
3.4 Temperature Dependency in Self-Refresh Mode 32
3.4.1 Retention Time with Temperature Dependency 33
3.4.2 Power Dissipation with Temperature Dependency 34
3.5 Previous Works 36
3.5.1 Replica-Cell based Self-Refresh Control Scheme 36
3.5.2 Sensor Based Self-Refresh Control Scheme 40
3.5.3 Temperature Sensor 44
Chapter 4 Proposed Scheme 47
4.1 Motivation of Proposed TASFR control Scheme 47
4.2 Structure of Proposed TASFR Control Scheme 48
4.2.1 Replica Cell Array Structure 49
4.2.2 Differential Sampling Structure 50
4.2.3 Adaptive Refresh Period Structure 51
4.3 Algorithm of Proposed TASFR Control Scheme 52
Chapter 5 Design considerations and Analyses 57
5.1 Design issues 57
5.1.1 Short Channel Effects (SCE) 58
5.1.2 Process Variations 60
5.2 Design considerations 62
5.2.1 Resolution 63
5.2.2 Resistor ladder 65
5.2.3 Comparator 68
5.3 Analyses of Proposed TASFR Control Scheme 70
5.3.1 Adaptive Refresh Period 71
5.3.2 Power Reduction in Self-Refresh mode 75
Chapter 6 Macro Implementation 76
6.1 Macro of Embedded-DRAM 76
6.1.1 Memory Cell Arrays 77
6.1.2 Peripheral Circuits 78
6.1.3 I/O Interface Circuits 79
6.2 Test Chip Design 80
Chapter 7 Measurement Results and Conclusions 82
7.1 Measurement Results 82
7.2 Summary and Conclusions 86
7.3 Future Works 89


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