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研究生:許逢文
研究生(外文):Shiu, Feng-Wen
論文名稱:堆疊式高介電係數阻擋層對電荷陷阱式快閃記憶體元件的影響
論文名稱(外文):Effects of Stacked High-k Blocking Layer on Charge-Trapping Flash Memory Devices
指導教授:張廖貴術
指導教授(外文):Chang-Liao, Kuei-Shu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:126
中文關鍵詞:阻擋層堆疊式
外文關鍵詞:FLASHCTF
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當浮動式閘極結構之快閃記憶體無法滿足元件微縮的發展時,SONOS-Type是取代浮動閘極結構的熱門候選者之一。而SONOS元件的穿遂氧化層厚度則大約是30?痋A就這樣的厚度而言,對於元件在可靠度方面的品質來說就會是一個問題,亦即,要如何在不改變穿遂氧化層厚度的前提之下,仍然能夠讓元件具有十年以上的電荷留存能力?並且在不犧牲資料留存能力的要求下在電性方面能有所提升,這些都是目前急需克服的問題。
本實驗將利用不同高介電係數材料以堆疊方式堆疊出SONOS元件的阻擋氧化層,研究主要是利用不同的材料具有不同的特性,配合堆疊式的結構,藉由不同的氮化程度、能隙大小的改變,K值的影響,堆疊厚度的改變等種種原因,利用能帶工程堆疊出最恰當的阻擋氧化層。
由實驗結果得知,以Al2O3/HfAlO結構做為阻擋氧化層,即先疊LOW-K再疊HIGH-K的阻擋層結構會有較佳的元件效能,以能隙觀點來看,第一層阻擋層先疊能隙較大的材料,第二層再疊K值較大,厚度較大的材料,可使得元件效能提升。同樣的,先疊一層高品質之二氧化矽再搭配不同的高介電係數做為阻擋氧化層,其元件特性也會表現得更好。實驗結果也可得知,元件經由PIII氮化技術可以減少HfO2材料在退火後之結晶化問題,進而提升電荷保持力,提升元件可靠度。

When floaging gate device can't satisfy smaller device, SONOS-Type is the one of candidate to replace it. SONOS-Type device tunneling layer thickness is about 30A ,it is a problem for retention. How to improve our device performance is very important.
In our experiment, using various high-k dielectrics as stacked SONOS-Type blocking layer. Different materials has different performances , matching stacked structure by nitrogen treatment with distinct doses(2mins , 4mins, 8mins) , bandgap-engineering, k-value as a excellent blocking oxide layer.
For tunneling oxide, the application of multilayer dielectric stacks is promising to realize tunnel barrier engineering. With a suitable combination of stacked tunneling oxide(low-k/high-k),a lower operation voltage can be achieve.
Using Al2O3/HfAlO as blocking layer has better performance than other stacked structures. Take high bandgap material as first layer blocking layer ,and secondly stack higher k material can improve device performance.
Stacking a high quality film as blocking layer first and then stack various high-k materials by PIII nitrogen treatment can reduce crystallize and enhance retention , promote device reliability after high temperature annealing process.
第一章 序論
第二章 快閃記憶體元件操作方法
第三章 實驗規劃與元件製程
第四章 利用高品質二氧化矽搭配高介電係數材料之堆疊式阻擋層對電荷陷阱式快閃記憶體元件的影響
第五章 利用不同高介電係數材料與堆疊方式之堆疊式阻擋層對電荷陷阱式快閃記憶體元件之研究
第六章 堆疊式阻擋層經由電漿沈浸離子佈植方式氮化處理後對電荷陷阱式快閃記憶體元件特性的影響
第七章 高介電係數材料對堆疊式阻擋層對電荷陷阱式快閃記憶體元件操作特性之研究
第八章 結論與建議

[1] Chih-Hao Cheng and Joseph Ya-Min Leea et al.,”Metal/high-k/high-k/oxide /semiconductor capacitors and field effect transistors using Al/La2O3/Ta2O5 /SiO2 /Si structure for nonvolatile memory applications,”Applied Physics Letter,91,pp.192903~192903-3,2007

[2] S. Choi, M. Cho, H. Hwang et al., “Improved metal oxide nitride oxide silicon type flash device with high-k dielectrics for blocking layer,” Journal of Applied Physics, vol. 94, no. 8, pp. 5408-5410, Oct, 2003.

[3] J. Sanghun, H. Jeong Hee, L. Junghoon et al., “Impact of metal work function on memory properties of charge-trap flash memory devices using fowler-nordheim P/E mode,” Electron Device Letters, IEEE, vol. 27, no. 6, pp. 486-488, 2006.

[4] Jiankang Bu, et al., “Retention reliability enhanced SONOS NVSM with scaled programming voltage”, IEEE Aerospace Conference paper, Vol.5, P5-2383 5-2390,2001

[5] Marvin H. White, et al., “A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol.20, No.2, Page(s): 52 - 57 ,JUNE 1997.

[6] W. J. Tsai, et al., “Data retention behavior of a SONOS type two-bit storage flash memory cell”, IEEE International Electron Devices Meeting, Page(s): 32.6.1 - 32.6.4 ,2001

[7] Verma, et al., ”Reliability Performance of ETOX Based Flash
Memory”, International Reliability Physics Symp, P.158, 1998.

[8] Haddad, et al., ”Degradation Due to Hole Trapping in Flash Memory Cells”, IEEE Electron Dev. Lett., Vol.10, No3, P.117, Mar. 1989.

[9] Adam Brand, et al., ”Novel Read Distub Failure Mechanism Induced by Flash Cycling”, International Reliability Physics Symp., P.127, 1993.


[10] Y. N. Tan, W. K. Chim, W. K. Choi et al., “Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation,” IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 654-662, Apr, 2006.

[11] W. Ensinger " Semiconductor processing by plasma immersion ion implantation." Materials Science and Engineering A, Volume 253, Issues 1-2, , Pages 258-268, 30 September 1998

[12] Takahiro Ohnakado, Hiroshi Onoda, Osamu Sakamoto, Kiyoshi Hayashi, Naho Nishioka,Hiroshi Takada, Kazuyuki Sugahara, Natsuo Ajika, and Shin-ichi Satoh et al,” Device Characteristics of 0.35 m P-Channel DINOR Flash Memory Using Band-to-Band Tunneling- Induced Hot Electron (BBHE) Programming,” IEEE Transactions on Electron Devices, vol. 46, no. 9, Page(s): 1866 - 1871 SEPTEMBER 1999

[13] Y. J. Zhao, X. N. Wang, H. L. Shang et al., “A low voltage SANOS nonvolatile semiconductor memory (NVSM) device,” Solid-State Electronics, vol. 50, no. 9-10, pp. 1667-1669, Sep-Oct, 2006.

[14] M. H. Cho, D. W. Moon, S. A. Park et al., “Interfacial characteristics of N-incorporated HfAlO high-k thin films,” Applied Physics Letters, vol. 84, no. 25, pp. 5243-5245, Jun, 2004.

[15] P. C. Jiang, Y. S. Lai, and J. S. Chen, “Influence of nitrogen content in WNx on its thermal stability and electrical property as a gate electrode,” Journal of the Electrochemical Society, vol. 153, no. 6, pp. G572-G577, 2006.

[16] S. Choi, M. Cho, H. Hwang et al., “Improved metal/oxide/nitride/oxide/silicon type flash device with high-k dielectrics for blocking layer,” Journal of Applied Physics, vol. 94, no. 8, pp. 5408-5410, Oct, 2003.

[17] P. H. Tsai, K. S. Chang-Liao, H. Y. Kao et al., "Improved electrical characteristics of high-k gated MOS devices by nitrogen incorporation with plasma immersion ion implantation (PIII)."ISDRS ,pp. 2192-2195.



[18] T. M. Pan, and W. W. Yeh, “High-performance high-k Y2O3 SONOS-Type flash memory,” Ieee Transactions on Electron Devices, vol. 55, no. 9, pp. 2354-2360, Sep, 2008.

[19] T. Erlbacher, A. J. Bauer, and H. Ryssel, "Hafnium silicate as control oxide in non-volatile memories." IEEE Transactions on Electron Devices ,pp. 2239-2242 , 2006

[20] G. Molas, M. Bocquet, J. Buckley, H. Grampeix, M. G?翼y et al., “Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories,” Microelectronic Engineering, Volume 85, Issue 12 , Pages 2393-2399, December 2008

[21] Y. Q. Wang, W. S. Hwang, G. Zhang et al., “Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3N4 tunneling layer,” IEEE Transactions on Electron Devices, vol. 54, no. 10, pp. 2699-2705, Oct, 2007.

[22] Breuil, L.; Furnemont, A.; Rothschild, A.; Van den bosch, G.; Cacciato, A.; Van Houdt, J.;” Improvement of TANOS NAND Flash Performance by the Optimization of a Sealing Layer ”NVSMW/ICMTD 2008. Joint. pp.126-127

[23] Yan Ny Tan; Chim, W.K.; Wee Kiong Choi; Moon Sig Joo; Byung Jin Cho;” Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation ” IEEE Transactions on Electron Devices Volume: 53 , Issue: 4 , Page(s): 654 – 662, 2006

[24] P.D.Kirsch,; M.A.Quevedo,; G.Pant,; S.Krishnan et al.,” Relationship of HfO2 Material Properties and Transistor Performance ” VLSI Technology, Systems, and Applications, Page(s): 1 - 2, 2006

[25] Ho-Myoung An, et al.,” Direct comparison of the electrical properties in metal/oxide/nitride/oxide/silicon and metal/aluminum oxide/nitride/oxide/silicon capacitors with equivalent oxide thicknesses” Thin Solid Films, Volume 517, Issue 18, Pages 5589-5592, 31 July 2009

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