臺灣博碩士論文加值系統

This work presents a column level binning circuit for a CMOS image sensor for the purpose of low-light imaging. A 2 x 2 kernel pixel binning (averaging) is employed in this design reducing the spatial resolution to 1/4 of the original size and every two columns of the pixel array share one binning circuit. The output signal of each pixel is sampled unto the binning circuit basically composed of two adjacent correlated double sampling circuit averaged by means of a row average switch. A 0.18μm TSMC process was used to simulate the circuit and simulation results reveal a kernel averaging error of less than or equal to 2% for low-light conditions with a power consumption of 123.9μW.

The ADC was designed using a single-slope A/D conversion topology with a simple circuit structure to effectively reduce area and power consumption. The designed ADC was compatible for both non-binning mode and binning mode. It has a correlated double sampling stage to eliminate fixed-pattern noise and extract the photoelectric data by subtracting the reset and signal values from the pixel or the averaged signal values from binning circuit. FFT simulation results reveal an ENOB of 7.3 bits for typical condition (TT, 55oC), a power consumption of 128.5μW per column ADC array and a power consumption of 258.4μW for the binning circuit and its output incorporated with two column ADCs. The frame rate for the CMOS image sensor is 84 fps.

TABLE OF CONTENTS

Acknowledgment…………………………………………………………i
Abstract....................................................................................................iv
Table of Contents……………………………………………………..vi
List of Figures……………………………………………………………ix
List of Tables……………………………………………………………xiii

Chapter 1: Introduction…………………………………………………….1
1.1 Background………………………………………………………..1
1.2 Motivation…………………………………………………………2
1.3 Thesis Organization………………………………………………..3

Chapter 2: Background and Overview……………………………………..4
2.1 CCD vs CMOS……………………………………………………4
2.1.1 Responsitivity……………………………………………….4
2.1.2 Dynamic Range……………………………………………..5
2.1.3 Uniformity…………………………………………………..5
2.1.4 Speed………………………………………………………..6
2.1.5 Windowing………………………………………………….6
2.1.6 Anti-blooming………………………………………..…….6
2.1.7 Biasing and Clocking………………………………………..6
2.2 CMOS Image Sensor Concept and Architecture………………….7
2.2.1 Pixel Array…………………………………………………..7
2.2.1.1 Passive Pixel………………………………………….8
2.2.1.2 Photodiode Active Pixel………………………………8
2.2.1.3 Photogate Active Pixel………………………….……9
2.2.2 Analog Signal Processing………………………………….10
2.2.2.1 Fixed Pattern Noise (FPN)…………………………..10
2.2.2.2 Correlated Double Sampling………………………...11
2.2.2.3 Double Delta Sampling………………..................….12
2.2.3 Readout Methods…………………………………………..13
2.2.3.1 CCD Image Sensor………………………………….13
2.2.3.2 CMOS Image Sensor………………………………..14
2.2.4 ADC Architectures…………………………….…………...15
2.2.4.1 Single Slope ADC……………………………..…….16
2.2.4.2 Frame Rate…………………………………………..18
2.3 Binning in CMOS Technology……………………………….….19

Chapter 3: Binning Circuit……………………………………….……….22
3.1 Pixel Architecture……………………………………………….22
3.2 Non-binning Mode………………………………...…………….26
3.3 Binning Mode…………………………………...……………….27
3.3.1 Sample and Hold……………………………….………….27
3.3.2 Charge Injection………………………………...………….28
3.3.3 Pixel Averaging…………………………………………….30
3.3.4 Signal Generation for Binning Circuit……………….…….40
3.3.5 Simulation for Binning Operation……………………...….43

Chapter 4: Single Slope ADC with CDS…………….. …………………..50
4.1 Ramp Generator………………………………………………….50
4.1.1 Adaptive Ramp Generation……………………………….53
4.1.2 Two-Stage Operational Amplifier…………….……….….54
4.2 Correlated Double Sampling …………………………………....58
4.3 Comparator………………………………………………..……..63
4.4 Multistage Comparator…………………………………………..65
4.5 Buffer/Quantizer………………………………………………....68
4.6 10-bit Synchronous Counter………………………………….….69
4.7 Static Latch………………………………………...…………….71
4.8 Shift Register…………………………………………………….72
4.9 Current Reference………………………………………….…….74
4.10 Signal Generation for ADC…………………………….……….76
4.11 ADC FFT Simulation………………………………...………….79

Chapter 5: Conclusion and Future work…………………………………. 85
5.1 Conclusion……………………………………………………......85
5.2 Future work………………………………………………………86

References…………...……………………………………………………87













LIST OF FIGURES

Figure 2.1a Passive pixel architecture……….……...………...……………9
Figure 2.1b Photodiode active pixel architecture……...……...……………9
Figure 2.1c Photogate active pixel architecture………....…………………9
Figure 2.2 Correlated double sampling method………....………..………11
Figure 2.3 Double delta sampling method………...…..…………….……12
Figure 2.4a CCD image sensor readout scheme……….....……………….14
Figure 2.4b CMOS image sensor readout scheme……..…...….…………14
Figure 2.5a ADC integration in pixel………...………...…….……...……16
Figure 2.5b ADC integration per column……………….…...……………16
Figure 2.5c ADC integration per chip……….........................……………16
Figure 2.6 Single slope ADC..………...…………………………..………18
Figure 2.7 Single slope ADC operation………...…………………………18
Figure 2.8 Multiple binning architectures………...……...…………….…20
Figure 2.9a CMOS binning techniques Frame transfer…...………………21
Figure 2.9b CMOS binning techniques Column level…...………………21
Figure 3.1a 4T pixel architecture………………………….………………22
Figure 3.1b 4T pixel equivalent circuit…………………...………………22
Figure 3.2a 4T pixel operation reset mode..................................................23
Figure 3.2b 4T pixel operation transfer mode.............................................23
Figure 3.3 4T pixel equivalent circuit for simulation..................................25
Figure 3.4a Non-binning mode 1st row readout……….......…..………..…26
Figure 3.4b Non-binning mode 2nd row readout………....………….……26
Figure 3.4c Non-binning mode column-level implementation...…………26
Figure 3.5a Sample and hold circuit………...………….……....…………27
Figure 3.5b S/H charge injection………...…………………….……….…27
Figure 3.6a SC model of a 2x2 pixel averaging…………….….…………31
Figure 3.6b Row banks for 2x2 pixel averaging………………...………31
Figure 3.6c Timing sequence………..…………………………...……..…31
Figure 3.7a Spatial resolution without binning………...………..…..……32
Figure 3.7b Spatial resolution with binning………...………….…………32
Figure 3.8a Binning mode 1st row readout………...…………..…….……33
Figure 3.8b Binning mode 2nd row readout………....………….…………33
Figure 3.8c Binning mode after binning process………...…….…………33
Figure 3.8d Binning mode column-level implementation……...…………33
Figure 3.9a Binning S/H model transistor level ………………...…..……34
Figure 3.9b Binning S/H model when SW1 turns on. ………...……….…34
Figure 3.10a Analog buffer schematic……………………………….……35
Figure 3.10b Analog buffer bulk connected to Vdd……...…...……..……35
Figure 3.10c Analog buffer bulk connected to source………..…...………35
Figure 3.11a Analog buffer with S/H bulk to Vdd……...…...……………36
Figure 3.11b Analog buffer with S/H bulk to its source……..……………36
Figure 3.12 Binning circuit……….........…………………..…………..…37
Figure 3.13 Timing sequence for binning circuit………...….……………38
Figure 3.14 Signal generation for Csel, Crst and Csig………...……….…41
Figure 3.15 Signal generation for Ca and Rca………...…….……………41
Figure 3.16 Signal generation for Ra, Sr1, Ss1, Sr2, Ss2 and Rsh…..…....42
Figure 3.17 Generated timing sequence for the binning circuit..…………42
Figure 3.18 Timing sequence for the binning circuit……….………….…43
Figure 3.19 Binning output comparison for low-light level……...…….…48
Figure 3.20 Binning circuit comparison for adjacent columns………...…48
Figure 3.21 Binning circuit layout…...………………………………...…49
Figure 4.1 Block diagram of the CDS/SS ADC………...…………….…..50
Figure 4.2 Basic principle of ramp generation………...…………….....…51
Figure 4.3 Basic ramp generator………...……………………………..…52
Figure 4.4 Basic ramp generator output with process variation………..…52
Figure 4.5 Adaptive ramp generator………..…...………….………..…..53
Figure 4.6 Two-stage operational amplifier ………...………………....…55
Figure 4.7 Two-stage operational amplifier (TT) ………...…………....…55
Figure 4.8 Adaptive ramp voltage generation………...………………......57
Figure 4.9 Adaptive ramp generator output with process variation….…...58
Figure 4.10 Correlated double sampling stage………...…………..……...59
Figure 4.11 Reset sampling phase………...………………………………59
Figure 4.12 Signal sampling phase………...……………………..…….…60
Figure 4.13 Ramping phase………...…………………………………..…60
Figure 4.14 CDS for non-binning and binning………...…………….……61
Figure 4.15 CDS for non-binning mode………...…………………..….…62
Figure 4.16 CDS for binning mode………...………………….….………62
Figure 4.17 Comparator………...………………………………….…..…63
Figure 4.18 Comparator gain and bandwidth...…………………………65
Figure 4.19 Multistage comparator to eliminate charge injection errors…66
Figure 4.20 Three-stage fully differential multistage comparator……...…66
Figure 4.21 Multistage comparator timing sequence………...….…...…...67
Figure 4.22 Three-stage comparator output………...……………………68
Figure 4.23 Buffer/Quantizer………...…………...................................…69
Figure 4.24 Buffer/Quantizer operation………...………………………69
Figure 4.25 A 10-bit synchronous counter………...……………..….……70
Figure 4.26 10-bit synchronous counter operation………...……………...70
Figure 4.27 Negative edge triggered static latch………...…………….….71
Figure 4.28 Negative edge triggered static latch operation………...…..…72
Figure 4.29 Parallel to serial shift register………...……………………...73
Figure 4.30 Parallel to serial shift register operation………...…………...74
Figure 4.31 Constant-gm current reference circuit………...…………..…75
Figure 4.32 Signal generation for Rst1, Sd and Rstc………...…………...77
Figure 4.33 Signal generation for Rst2, Rst3, Step and Stepb………..…..77
Figure 4.34 Signal generation for Srp and Srpb………...………….……..78
Figure 4.35 Signal generation for Sorp and Rstsr………...………………78
Figure 4.36 Generated timing sequence for the ADC circuit………..……79
Figure 4.37 SNR FFT plot (SS, 85oC) ………...……………………….…83
Figure 4.38 SNR FFT plot (TT, 55oC) ………...………………….………83
Figure 4.39 SNR FFT plot (FF, 27oC) ………...………………….………84
Figure 4.40 Single Slope CDS Stage Layout….………………….………84

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