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研究生:黃彥筌
研究生(外文):Yen-Chuan Huang
論文名稱:奈米級互補式金氧半製程之管線式類比數位轉換器設計
論文名稱(外文):The Design of Nanometer CMOS Pipelined A/D Converter
指導教授:李泰成
指導教授(外文):Tai-Cheng Lee
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:英文
論文頁數:107
中文關鍵詞:類比數位轉換迴圈式類比數位轉換器管線式類比數位轉換器運算放大器分享技巧時間分享技巧
外文關鍵詞:analog-to-digital conversioncyclic ADCpipelined ADCopamp-sharing techniquetime-sharing technique
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類比數位轉換器是連接真實世界與離散運算領域的關鍵元件,此篇論文主要介紹迴圈式與管線式類比數位轉換器之設計,以類比的方式,達到小面積、低功率消耗等設計目標。

在本篇論文中,首先提出並分析一個以部分正回授迴圈為架構之乘二電路,其次介紹應用此電路之迴圈式類比數位轉換器的設計與工作原理。由於此轉換器之殘值計算與取樣相位的結合,故只需四個時脈週期,即可完成九位元的轉換,與通常需要十個時脈週期的傳統架構相較,轉換延遲大幅縮短。提出之架構已於九十奈米製程中實現;電路核心所佔的晶片面積只有0.02平方毫米,是目前相似解析度的類比數位轉換器裡,晶片面積最小的設計。實驗量測結果顯示,當轉換頻率為五千萬赫茲時,信噪失真比(SNDR)約為50.5分貝,核心電路功率消耗則約為6.9毫瓦。

接著是介紹一個時間分享的技巧來降低管線式類比數位轉換器整體的功率消耗,改善傳統運算放大器分享架構之功率效益。所設計之類比數位轉換器只需要一個運算放大器就可以完成十位元的轉換。提出之架構也於九十奈米製程中實現;電路核心所需要的晶片面積為0.058平方毫米。實驗量測結果顯示,當轉換頻率為一億赫茲時,信噪失真比(SNDR)約為55.0分貝,而核心功率消耗約為4.5毫瓦。

最後一個設計則是並聯前述之十位元轉換器,將轉換頻率進一步提升,達到四億赫茲。實驗量測結果顯示,信噪失真比(SNDR)約為53.0分貝,而整體功率消耗約為36毫瓦。


Analog-to-digital (A/D) converters which provide the link between the analog world and digital domain represent important building blocks in many systems. In this dissertation, three ADCs are presented to achieve small-area and low-power design objectives with analog approaches.
First, a 9-bit cyclic ADC employs a novel multiply-by-two circuit for enhancing the speed of residue evaluation is presented. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform a 9-bit conversion. The proposed 0.02-mm2 ADC has been fabricated in 90-nm digital CMOS technology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB with a core power consumption of 6.9 mW from a 1.0-V supply.
Then, a 10-bit pipelined ADC employs both opamp and time sharing techniques to reduce the power consumption and silicon area is proposed. This ADC needs only one opamp to complete the 10-bit conversion. The prototype design also has been fabricated in 90-nm digital CMOS technology and occupies only 0.058 mm2. It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the core power consumption is 4.5 mW from a 1.0-V supply.
The last work was an extension of the second design. The conversion rate is efficiently boosted by four ADCs in parallel. The measured results give an SNDR of 53.0 dB and power consumption of 36 mW at a sampling rate of 400 MHz.


誌謝 i
摘要 iii
Abstract iv
Contents v
List of Figures ix
List of Tables xiii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization 2
Chapter 2 Fundamentals of Analog-to-Digital Converters 5
2.1 Introduction 5
2.2 ADC Performance Metrics 5
2.2.1 Differential and Integral Nonlinearity (DNL, INL) 5
2.2.2 Signal-to-Noise Ratio (SNR) 8
2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 9
2.2.4 Effective Number-of-Bits (ENOB) 10
2.2.5 Spurious-Free Dynamic Range (SFDR) 10
2.2.6 Figure of Merit (FoM) 11
2.3 Architectures of Analog-to-Digital Converters 11
2.3.1 Flash Architecture 12
2.3.2 Two-Step and Sub-Ranging Architecture 13
2.3.3 Pipelined Architecture 15
2.3.4 Cyclic (Algorithmic) Architecture 16
2.4 Digital Error Correction 17
2.4.1 Out of Range Error 18
2.4.2 Over Range Error Correction 18
2.4.3 1.5-Bit Pipelined Stage 22
2.5 Summary 26
Chapter 3 A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS 27
3.1 Introduction 27
3.2 Conventional Cyclic ADC Architecture Review 28
3.3 Proposed Architecture 30
3.3.1 Settling Time of the Proposed Cyclic Stage 33
3.3.2 Current-Switching Track-and-Hold 37
3.3.3 Timing for the Cyclic ADC 41
3.3.4 Track-and-Evaluation Characteristic 42
3.4 Experimental Results 44
3.5 Summary 51
Chapter 4 A 10-bit 100-MS/s Pipelined ADC with a Time-Sharing Technique 53
4.1 Introduction 53
4.2 Time-Sharing Technique 56
4.3 Circuit Implementation 60
4.3.1 Input Sampling Network 60
4.3.2 Opamp Design 62
4.3.3 Capacitor Sharing Technique 66
4.4 Experimental Results 71
4.5 Summary 78
Chapter 5 A 10-bit 400-MS/s Interleaved Pipelined ADC 79
5.1 Interleaved Architecture 79
5.1.1 Offset Errors 80
5.1.2 Gain Mismatch 81
5.1.3 Phase Skew 82
5.2 Circuit Implementation 84
5.2.1 Track-and-Hold (T/H) Buffer 85
5.2.2 Gain/Offset Mismatch Correction 87
5.3 Simulation Results 89
5.4 Experimental Results 91
5.5 Summary 94
Chapter 6 Conclusions 97
Bibliography 99
Publication List 107


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