本論文之目的在於研究使用商用標準金氧半場效電晶體(CMOS)製程來設計可供單頻及多頻段使用之低雜訊放大器。低雜訊放大器常於無線通訊系統之接收端扮演了決定整個系統的雜訊指數之重要角色，在射頻電路中的地位不可或缺。近年來，使用CMOS製程研製單頻帶之低雜訊放大器的技術已漸趨成熟。然而隨著無線通訊頻帶的開放，未來單一行動通訊裝置勢必將需具備可支援多個不同頻帶之功能。因此本論文之研究重心便在於使用單一晶片實現寬頻抑或是多頻帶之低雜訊放大器。
首先實現的是一個使用TSMC 0.18μm CMOS製程所製作之2.4/ 5.2 GHz切換式雙頻帶低雜訊放大器。其於2.4 GHz的增益可達 8.8 dB，雜訊指數為3.4 dB；於5.2 GHz的增益為10.4 dB，雜訊指數為5.5 dB。此頻帶主要是應用於無線網路通訊的IEEE 802.11 a/b/g/n 頻段通訊，同時2.4 GHz亦屬ISM頻段，與更多的通訊設備更能相容。
其次是一個使用TSMC 0.18μm CMOS製程所製作之5.2~11.2 GHz低雜訊放大器。在此3-dB頻寬當中，最高的增益為13.9 dB，最低雜訊指數為4.9 dB。此頻帶可支援聯邦通訊協定 (FCC) 所認可之UWB (3.1 - 10.6 GHz) 頻段應用。
最後為一個使用TSMC 90nmLP CMOS製程所製作之24/77 GHz同時式雙頻帶低雜訊放大器。利用所提出的電路架構，可以實現任意雙頻帶的低雜訊放大器。

The purpose of this thesis is to develop single-band and multi-band low noise amplifiers employing commercial standard CMOS processes. The low noise amplifier in the receiver usually plays an important roles in determining the noise figure of the whole wireless communication system, and it is irreplaceable in RF circuits. Recently, techniques for designing single-band CMOS low noise amplifiers have been more and more mature. However, as more wireless communication frequency bands are released and approved, one single mobile device should support multi-band usages in the future. As a result, the researches of this thesis highly focus on designing wideband or multiband low noise amplifiers in one single chip.
First, an implementation of a 2.4/5.2 GHz switchable dual band low noise amplifier using TSMC 0.18μm CMOS process is presented. It achieves a small signal gain of 8.8 dB and noise figure of 3.4 dB in 2.4 GHz; on the other hand, it achieves a small signal gain of 10.4 dB and noise figure of 5.5 dB in 5.2 GHz. This is mainly for IEEE 802.11 a/b/g/n frequency applications in wireless network communication. Furthermore, the 2.4 GHz band also lies in the ISM (industrial, scientific and medical ) band applications.
Second, an implementation of a 5.2 - 11.2 GHz low noise amplifier using TSMC 0.18μm CMOS process is presented. It achieves the highest gain of 13.9 dB and the lowest noise figure of 4.9 dB in its 3-dB bandwidth. This frequency band supports the 3.1 - 10.6 GHz UWB (ultra-wideband) approved by the Federal Communications Commission (FCC).
Finally an implementation of a 24/77 GHz concurrent dual band low noise amplifier using TSMC 90nmLP CMOS process is presented. With the proposed circuit topology, dual-band LNAs operating at any two frequencies can be achieved.

口試委員會審定書 #
誌謝 i
摘要 ii
ABSTRACT iii
CONTENTS v
LIST OF FIGURES viii
LIST OF TABLES xiii
Chapter 1 Introduction 1
1.1 Motivation......................................................................................................1
1.2 Literature Survey............................................................................................2
1.2.1 Ultra-wideband Low Noise Amplifiers.................................................2
1.2.2 Dual-band Low Noise Amplifiers.........................................................5
1.3 Contributions .................................................................................................8
1.4 Thesis Organization......................................................................................10
Chapter 2 Basics of Wide-band and Multi-band Low Noise Amplifiers 11
2.1 Basics of Low Noise Amplifier 12
2.1.1 Microwave Amplifier Design 12
2.1.2 Noise. 14
2.2 Common Topologies for Wide-band LNAs 19
2.2.1 General Topologies..............................................................................19
2.2.2 Viewing the Cascode Topology as CS + CG.......................................21
2.2.3 Noise Canceling...................................................................................24
Chapter 3 Switchable Dual-band Low Noise Amplifier Design 27
3.1 Introduction 27
3.1.1 Go Wireless - Introduction to IEEE 802.11 a/b/g/n.............................27
3.1.2 Input broadband Impedance Matching................................................31
3.1.3 Dual Band System Topology...............................................................33
3.2 2.4/5.2 GHz Switchable Dual-band Low Noise Amplifier Design...............37
3.2.1 Device Topology..................................................................................37
3.2.2 Circuit Implementation........................................................................42
3.3 Experimental Results.....................................................................................44
3.3.1 Measurement Results...........................................................................44
3.3.2 Discussion............................................................................................51
3.4 Summary........................................................................................................61
Chapter 4 5.2-11.2 GHz Low Noise Amplifier Design...........................................62
4.1 Introduction...................................................................................................62
4.2 5.2-11.2 GHz Low Noise Amplifier Design..................................................63
4.2.1 Device Topology Selection..................................................................64
4.2.2 Circuit Implementation........................................................................66
4.3 Experimental Results.....................................................................................69
4.3.1 Measurement Results...........................................................................69
4.3.2 Discussion of the Coupling Effects Between Adjacent Inductors.....76
4.4 Summary........................................................................................................83
Chapter 5 Concurrent Dual-band Low Noise Amplifier Design..........................85
5.1 Introduction...................................................................................................85
5.1.1 Motivation...........................................................................................85
5.1.2 Input Matching....................................................................................86
5.1.3 Noise Matching....................................................................................88
5.1.4 Load Circuit, Output Matching, and Gain...........................................92
5.1.5 Dual Band Antenna..............................................................................93
5.2 Concurrent Dual-band Low Noise Amplifier Design....................................94
5.2.1 Device Topology..................................................................................94
5.2.2 Dual Bandpass Input and Output Matching........................................99
5.2.3 Dual Band Bypass.............................................................................101
5.2.4 Circuit Implementation......................................................................104
5.3 Experimental Results...................................................................................108
5.4 Summary......................................................................................................112
Chapter 6 Conclusions...........................................................................................114
REFERENCES.............................................................................................................116

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